Internal timing method and circuit for programmable memories

Details Internal timing method and circuit for programmable memories Internal timing method and circuit for programmable memories

1995-02-21

1997-09-02

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365195, 3652257, G11C 700

Patent

active

056639210

ABSTRACT:
A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

REFERENCES:
patent: 4425633 (1984-01-01), Swain
patent: 4687951 (1987-08-01), McElroy
patent: 4970418 (1990-11-01), Masterson
patent: 5054002 (1991-10-01), Ninomiya et al.
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5381379 (1995-01-01), Fukumoto
patent: 5424985 (1995-06-01), McClure et al.

Affiliated with

Also associated with

Rating

Internal timing method and circuit for programmable memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Internal timing method and circuit for programmable memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal timing method and circuit for programmable memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-313845