Internal timing circuit for a CMOS programmable logic array

Details Internal timing circuit for a CMOS programmable logic array Internal timing circuit for a CMOS programmable logic array

1989-06-15

1991-02-05

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307465, 307481, 307246, H03K 19177

Patent

active

049908014

ABSTRACT:
A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.

REFERENCES:
patent: 4675556 (1987-06-01), Bazes
patent: 4697105 (1987-09-01), May
patent: 4740721 (1988-04-01), Chung et al.
patent: 4760290 (1988-07-01), Martinez
patent: 4769562 (1988-09-01), Ghisio
patent: 4831285 (1989-05-01), Gaisen
patent: 4894564 (1990-01-01), Sakashita et al.
Patent Abstracts of Japan, Book 10, No. 283 (E-440); and JP-A-61 101 124 (Hitachi Micro Computer Eng Ltd).
N. H. E. Weste et al.; "Principles of CMOS VLSI Design", 1985, Section 372-373; Addison-Wesley Publishign Company, Reading, Mass., U.S.

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