Internal time-out circuit for CMOS dynamic RAM

Details Internal time-out circuit for CMOS dynamic RAM Internal time-out circuit for CMOS dynamic RAM

1984-07-26

1987-11-17

Heyman, John S.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307451, 307246, 307273, H03K 3284, H03K 5153, H03K 19094, H03K 1730

Patent

active

047076267

ABSTRACT:
A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The RC delay circuit uses an MOS transistor as the resistor, with the gate of this device connected to the supply voltage, so the resistance varies with changes in the supply. A CMOS inverter stage in the delay circuit has its input connected across the capacitor of the RC delay, so the trip point will vary with threshold voltage. In a dynamic RAM, this circuit may be used to establish the critical timing between write and read mode.

REFERENCES:
patent: 3504200 (1970-03-01), Avellar
patent: 3532993 (1970-10-01), Kennedy
patent: 3659214 (1972-04-01), Iijima
patent: 3761743 (1973-09-01), Barber
patent: 3772535 (1973-11-01), Tuten
patent: 4065721 (1977-12-01), Rabe
patent: 4277697 (1981-07-01), Hall et al.
patent: 4408168 (1983-10-01), Higuchi
Weil, "Feedback Triggers One-Shot from Both Polarity Edges", Electronics, p. 87, 7/20/1970.
Chung, "Multiphase One Shot Provides Pulses", Electronic Engineering, p. 21, 9/1976.

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