Internal synchronization type MOS SRAM with address transition d

Details Internal synchronization type MOS SRAM with address transition d Internal synchronization type MOS SRAM with address transition d

1989-03-29

1990-04-10

Fears, Terrell W.

Static information storage and retrieval

Addressing

36523006, 365233, G11C 1300

Patent

active

049166689

ABSTRACT:
A memory cell array includes a plurality of static memory cells arranged in a matrix form and selectively controlled by means of word lines to output complementary memory data to paired bit lines. An address transition detecting circuit generates an address transition signal in the form of a monostable pulse having a constant length when detecting the transition of an address signal. A bit line initializing circuit initializes the potentials of the paired bit lines in synchronism with the address transition signal. A pulse width extension circuit sets the pulse width of the address transition signal generated from the address transition detecting circuit to be longer in the write mode than in the readout mode.

REFERENCES:
patent: 4811297 (1989-03-01), Ogawa

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