Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-01-30
2002-12-24
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S354000
Reexamination Certificate
active
06498469
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an internal supply voltage generating circuit and a method of generating an internal supply voltage. More particularly, it relates to an internal supply voltage generating circuit in a semiconductor memory device and an internal supply voltage generating method, which generate an internal supply voltage by dropping an external supply voltage and provide the individual circuits of the semiconductor memory device with the generated internal supply voltage.
Due to the micronization of the wiring pattern and the reduction in power consumption, a semiconductor memory device is provided with an internal supply voltage generating circuit which drops an external supply voltage to generate an internal supply voltage to be supplied to the individual internal circuits. The internal supply voltage generating circuit includes a reference voltage generating circuit and a voltage-drop regulator.
The reference voltage generating circuit generates a desired reference voltage from the external supply voltage and supplies the reference voltage to the voltage-drop regulator. The voltage-drop regulator receives the reference voltage and the external supply voltage and generates a stable internal supply voltage by dropping the external supply voltage in accordance with the reference voltage. The voltage-drop regulator supplies the internal supply voltage to various internal circuits via internal power lines.
It is desirable that a variation in the internal supply voltage be as small as possible. Therefore, the reference voltage, which is supplied to the voltage-drop regulator, should preferably have a high precision. However, there is a current of several micro amperes flowing in the reference voltage generating circuit and the threshold values of the individual transistors of the reference voltage generating circuit are not constant due to a productional variation. This results in a variation in reference voltage.
As a solution to reduce the variation in reference voltage, an internal supply voltage generating circuit having an internal reference generating circuit connected between a reference voltage generating circuit and a voltage-drop regulator has been proposed. The internal reference generating circuit regulates the reference voltage to a desired voltage and supplies the regulated reference voltage to the voltage-drop regulator.
FIG. 1
is a schematic block diagram of a conventional internal supply voltage generating circuit
50
. The internal supply voltage generating circuit
50
includes a reference voltage generating circuit
51
, an internal reference generating circuit
52
and a voltage-drop regulator
53
.
The reference voltage generating circuit
51
generates a desired first reference voltage Vflat
1
from an external supply voltage Vcc and supplies the first reference voltage Vflat
1
to the internal reference generating circuit
52
. The internal reference generating circuit
52
generates a second reference voltage Vflat
2
using the first reference voltage Vflat
1
.
As shown in
FIG. 2
, the internal reference generating circuit
52
includes a differential amplifier
56
, a driver
57
, a trimming circuit
58
and a phase compensation circuit
59
.
The differential amplifier
56
includes a differential amplification section which comprises a first N channel MOS (NMOS) transistor Q
1
and a second NMOS transistor Q
2
, as shown in FIG.
3
. The sources of the NMOS transistors Q
1
and Q
2
are grounded via a current-controlling NMOS transistor Q
3
. The gate of the NMOS transistor Q
3
is connected to the gate of the first NMOS transistor Q
1
.
The drains of the NMOS transistors Q
1
and Q
2
are connected to an external supply voltage Vcc via P channel MOS (PMOS) transistors Q
4
and Q
5
respectively. The gates of the PMOS transistors Q
4
and Q
5
are connected together to the drain of the second NMOS transistor Q
2
.
The first reference voltage Vflat
1
from the reference voltage generating circuit
51
is supplied to the gate of the first NMOS transistor Q
1
. A feedback voltage Vf from the trimming circuit
58
is supplied to the gate of the second NMOS transistor Q
2
. The drain of the first NMOS transistor Q
1
also serves as the output terminal of the differential amplifier
56
, which is connected to the driver
57
.
The driver
57
includes a PMOS transistor Q
6
whose gate is supplied with an output voltage Vout of the differential amplifier
56
. The source of the PMOS transistor Q
6
is connected to the external supply voltage Vcc and the drain of the PMOS transistor Q
6
is connected to the voltage-drop regulator
53
. The second reference voltage Vflat
2
is supplied to the voltage-drop regulator
53
(in
FIG. 1
) from the drain of the PMOS transistor Q
6
. The drain of the PMOS transistor Q
6
is grounded via the trimming circuit
58
.
The trimming circuit
58
includes a voltage dividing circuit, which includes four resistors R
1
to R
4
, and a selection circuit. The selection circuit includes three transfer gates G
1
to G
3
, each connected between the individual nodes between one of the resistors R
1
-R
4
of the voltage dividing circuit and the gate of the second NMOS transistor Q
2
of the differential amplifier
56
. One of the three transfer gates G
1
-G
3
is turned on by selection signals &phgr;
1
to &phgr;
3
and the remaining two transfer gates are turned off.
The divided voltage, which is produced by the voltage dividing circuit, is supplied via the turned-on transfer gate to the non-inverting input terminal (the gate of the second NMOS transistor Q
2
) of the differential amplifier
56
as the feedback voltage Vf.
The drain of the PMOS transistor Q
6
is grounded via the phase compensation circuit
59
. The phase compensation circuit
59
includes a resistor R
5
and a capacitor Cl.
The differential amplifier
56
regulates the second reference voltage Vflat
2
by raising or lowering the output voltage, such that the feedback voltage Vf substantially coincides with the first reference voltage Vflat
1
. That is, the differential amplifier
56
detects whether the second reference voltage Vflat
2
is a predetermined voltage during a test conducted before shipment. When the second reference voltage Vflat
2
is not the predetermined voltage, one of the three transfer gates G
1
-G
3
is turned on to regulate the feedback voltage Vf, so that the second reference voltage Vflat
2
is adjusted to the predetermined voltage. Therefore, (the voltage-drop regulator
53
produces a highly accurate and stable internal supply voltage Vdd in accordance with the second reference voltage Vflat
2
whose productional variation has been compensated.
The phase compensation circuit
59
prevents the internal reference generating circuit
52
from performing an oscillating operation due to the phase shift of the feedback voltage Vf supplied to the differential amplifier
56
.
A semiconductor memory device has a plurality of internal supply voltage generating circuits according to the usage of the internal supply voltage Vdd (e.g., the supply voltage for peripheral function circuits, the supply voltage for memory core circuits). Specifically, because of various factors such as the problems related to the withstand voltage and power consumption, which originat from the micro-fabrication process, power supply noise and the set level of the voltage-drop potential, a semiconductor memory device has an internal supply voltage generating circuit for input/output circuits, an internal supply voltage generating circuit for peripheral function circuits and an internal supply voltage generating circuit for a memory array, which are independently provided.
As shown in
FIG. 4
, a plurality of internal reference generating circuits
64
,
65
and
66
are connected to one reference voltage generating circuit
51
, and a plurality of voltage-drop regulators
61
,
62
and
63
are respectively connected to the internal reference generating circuits
64
,
65
and
66
. The internal reference generating circuits
64
,
6
Arent Fox Kinter Plotkin & Kahn PLLC
Berhane Adolf Deneke
Fujitsu Limited
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