Internal supply voltage generating cicuit in a semiconductor...

Details Internal supply voltage generating cicuit in a semiconductor... Internal supply voltage generating cicuit in a semiconductor...

2001-01-30

2002-05-07

Riley, Shawn (Department: 2838)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C713S300000

Reexamination Certificate

active

06385119

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a semiconductor memory device, and, more particularly, to an internal supply voltage generating circuit of a semiconductor device for dropping an external supply voltage and generating an internal supply voltage provided to an internal circuit, as well as a method for controlling the same.
For decreasing the amount of current consumed, a semiconductor memory device is provided with two internal supply voltage generating circuits to generate internal supply voltages provided to internal circuits. A first internal supply voltage generating circuit (a large power voltage-drop circuit) consumes a relatively large current and supplies a relatively large driving power. A second internal supply voltage generating circuit (a small power voltage-drop circuit) consumes a relatively small current and supplies a relatively small driving power. In an active mode of the semiconductor memory device, the first and second internal supply voltage generating circuits operate and provide internal supply voltages to internal circuits. In a stand-by mode or a power-down mode, the first internal supply voltage generating circuit stops operating, and only the second internal supply voltage generating circuit provides an internal supply voltage to internal circuits. Since only the second internal supply voltage generating circuit operates, the power consumption of the semiconductor memory device is reduced.
In an active mode, the semiconductor memory device may assume a hold state in accordance with a command (active command) from an MPU (microprocessor unit) or a memory controller. For example, if a read command or a write command is not supplied during the period from when a word line is activated by an active command and a sense amplifier begins to operate to when the semiconductor memory device begins to perform a reset (precharge) operation, the semiconductor memory enters a state of an active pause. During the active pause period, power consumption is small because internal circuits include CMOS transistors, which have low power consumption.
However, during the active pause period, a large amount of current flows through the first voltage-drop regulator of the large power voltage-drop circuit, and it is desired to decrease the power consumption therein. For example, Japanese Patent Laid Open No. 7-105682 discloses a semiconductor memory device provided with a first regulator that in an active mode supplies a relatively large driving power to a sense amplifier during operation of the sense amplifier and a second regulator that, after operation of the sense amplifier, supplies a driving power smaller than that of the first regulator. Thus, in write and read operations after operation of the sense amplifier, a minimum required power is supplied, thereby decreasing the power consumption.
More particularly, the semiconductor memory device is provided with three voltage-drop regulators. In a stand-by mode, only one voltage-drop regulator is activated, while in an active mode all three voltage-drop regulators are activated, and the sense amplifier is made to rise rapidly. When the sense amplifier is stable after the lapse of a predetermined time, the semiconductor memory device enters a state of active pause, and the two voltage-drop regulators are inactivated and on stand-by for the next command operation.
However, since two voltage-drop regulators are still activated in an active pause, it is difficult to minimize power consumption of the internal supply voltage generating circuit. The provision of the three voltage-drop regulators also increases the circuit area and results in a more complicated control system.
FIG. 1
is a schematic block diagram of a conventional control circuit
100
for an internal supply voltage generating circuit and a row system circuit. In a memory cell area, a row system circuit
41
is provided for activating a word line and a row decoder, and an internal supply voltage is provided to the row system circuit
41
from a large power voltage-drop regulator
42
. The control circuit
100
includes a command detecting circuit
43
, a row control circuit
44
, a regulator control circuit
50
, which acts as an activating signal generating circuit and controls the large power voltage-drop regulator
42
, and an active time-out circuit
80
.
The command detecting circuit
43
receives an external command, such as chip select signal, row address strobe signal, column address strobe signal, and write enable signal, from external devices (not shown) and detects various commands in accordance with combinations of the signals.
Upon detection of a refresh command, the command detecting circuit
43
provides a row command signal rowz having a high level to the row control circuit
44
and provides a refresh command signal refz having a high level to the active time-out circuit
80
.
In response to the row command signal rowz having a high level, the row control circuit
44
produces a row control signal brasz having a high level and subsequently produces a word line activating signal plez having a high level as a memory cell area activating signal, slightly behind the row control signal brasz.
In accordance with the row control signal brasz at high level, the regulator control circuit
50
produces an activating signal enz at high level to activate the large power voltage-drop regulator
42
. In response to the word line activating signal plez at high level, the regulator control circuit
50
causes the activating signal enz to fall when the semiconductor device enters an active pause state upon lapse of time t
1
after the rise of the activating signal enz.
The row system circuit
41
is activated by the row control signal brasz at high level provided from the row control circuit
44
. At this time, a relatively large driving power is provided to the row system circuit
41
from the activated large power voltage-drop regulator
42
, so that the row system circuit operates at a high speed. When the row system circuit
41
is stable, the large power voltage-drop regulator
42
is inactivated, and a driving power is provided to the row system circuit
41
from a small power regulator (not shown).
When the refresh command signal refz at high level is supplied from the command detecting circuit
43
, the active time-out circuit
80
provides an active time-out signal tout at low level to the row control circuit
44
upon lapse of a predetermined time t
2
after the supply of the word line activating signal plez at high level from the row control circuit
44
.
In response to the active time-out signal tout at low level, the row control circuit
44
causes the row control signal brasz to fall, thereby inactivating the row system circuit
41
. The row control circuit
44
causes the row control signal brasz and the word line activating signal plez to fall, and in response to the activating signal plez, the active time-out circuit
80
causes the active time-out signal tout to rise. Thus, the row control circuit
44
is ready for the next refresh operation.
As shown in
FIG. 2
, the regulator control circuit
50
includes a detector circuit
51
and a delay circuit
52
. The detector circuit
51
is an exclusive OR circuit including three NAND circuits
53
,
54
,
55
and three inverter circuits
56
,
57
,
58
. When the row control signal brasz and the word line activating signal plez have different levels from each other, the detector circuit
51
provides a detection signal eor at low level to the delay circuit
52
. The first NAND circuit
53
receives the word line activating signal plez and the row control signal brasz, which has been inverted by the first inverter circuit
56
. The second NAND circuit
54
receives the row control signal brasz and the word line activating signal plez, which has been inverted by the second inverter circuit
57
. The third NAND circuit
55
receives output signals from the first and second NAND circuits
53
,
54
. An output terminal of the third NAND circuit
5

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