Internal source clock generation circuit for use with power mana

Details Internal source clock generation circuit for use with power mana Internal source clock generation circuit for use with power mana

1998-06-25

2000-01-18

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327298, H03K 513

Patent

active

060160713

ABSTRACT:
A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and for bypassing the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and starts back up with a rising transition of the oscillations.

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