Internal read signal generator and semiconductor memory...

Details Internal read signal generator and semiconductor memory... Internal read signal generator and semiconductor memory...

2006-12-29

2009-06-16

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S292000, C327S293000

Reexamination Certificate

active

07548106

ABSTRACT:
The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.

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patent: 2003-0046133 (2003-06-01), None
patent: 10-2005-0121524 (2005-12-01), None

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