Internal potential generating circuit and boosted potential gene

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327537, 327589, H03K 301

Patent

active

059364599

ABSTRACT:
A first charge pumping circuit including a first capacitor and first and second switches, and a second charge pumping circuit including a second capacitor and third and fourth switches, are operated complementarily. The first capacitor is provided between first and second nodes, and the second capacitor is provided between third and fourth nodes. An NMOS transistor as equalizing means is provided between the first and third nodes. Before the start of supply of charges by the second switch to the second node and injection of charges by the third switch to an output node, the NMOS transistor is turned on, whereby potentials at the first and third nodes are equalized. Accordingly, the charges consumed by the first charge pumping circuit can be recycled by the second charge pumping circuit. Thus, lower power consumption is realized.

REFERENCES:
patent: 4736121 (1988-04-01), Cini et al.
patent: 5003197 (1991-03-01), Nojima et al.
patent: 5394026 (1995-02-01), Yu et al.
Dong-Jae Lee et al. A 35ns 64Mb DRAM Using On-Chip Boosted Power Supply, 1992 pp. 64-65.
Yasuhiko Tsukikawa et al., An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM'S, 1994 pp. 534-538.
R.C. Ross et al., Application of High-Voltage Pumped Supply for Low-Power DRAM, 1992 pp. 106-107.

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