Internal node offset voltage test circuits and methods

Details Internal node offset voltage test circuits and methods Internal node offset voltage test circuits and methods

2005-04-26

2005-04-26

Ramirez, Nestor (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06885211

ABSTRACT:
A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

REFERENCES:
patent: 5184162 (1993-02-01), Saitoh et al.
patent: 5861774 (1999-01-01), Blumenthal
patent: 6483338 (2002-11-01), Weng et al.
patent: 6504394 (2003-01-01), Ohlhoff

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