Internal loop-back architecture for parallel...

Details Internal loop-back architecture for parallel... Internal loop-back architecture for parallel...

2008-02-26

2010-06-22

Ferris, Derrick (Department: 2463)

Multiplex communications

Diagnostic testing

Loopback

Reexamination Certificate

active

07742427

ABSTRACT:
An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

REFERENCES:
patent: 7388904 (2008-06-01), Raghavan et al.
patent: 7526033 (2009-04-01), Sindalovsky et al.
patent: 2003/0149922 (2003-08-01), Lai
patent: 2006/0198315 (2006-09-01), Sasagawa et al.

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