Internal/external clock option for built-in self test

Details Internal/external clock option for built-in self test Internal/external clock option for built-in self test

1998-01-09

1999-02-23

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

365201, 371 2236, 371 225, 371 277, G06F 1126

Patent

active

058751530

ABSTRACT:
An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).

REFERENCES:
patent: 5222068 (1993-06-01), Burchand
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5732209 (1998-03-01), Vigil et al.
patent: 5761215 (1998-06-01), McCarthy et al.

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