Internal communication arrangement for a multiprocessor system

Details Internal communication arrangement for a multiprocessor system Internal communication arrangement for a multiprocessor system

1981-12-14

1985-09-24

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1516, G06F 304

Patent

active

045436274

ABSTRACT:
A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.

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McGlynn, Daniel R., Microprocessors: Technology, Architecture, Applications, pp. 182-185, 2/22/77.

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