Internal clock signal generation circuit including delay line, a

Details Internal clock signal generation circuit including delay line, a Internal clock signal generation circuit including delay line, a

1998-01-23

1999-08-31

Le, Vu A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 700

Patent

active

059462680

ABSTRACT:
An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.

REFERENCES:
patent: 5754490 (1998-05-01), Harrison et al.
patent: 5768177 (1998-06-01), Sakuragi
patent: 5805511 (1998-09-01), Manning
Shoji, "CMOS Digital Circuit Technology", pp. 177-189. 1997 IEEE International Solid-State Circuits Conference (Abstract).

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