Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-03-25
2001-09-18
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000, C327S161000, C331SDIG002, C375S376000
Reexamination Certificate
active
06292040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal clock signal generating circuit. More specifically, the present invention relates to an internal clock signal generating circuit for generating, in synchronization with an externally applied clock signal, signals which are multiplication of the externally applied clock signal.
2. Description of the Background Art
As speed of operation of microprocessors has been ever increasing, increase in speed of internal clock signals for operating overall system including a semiconductor memory device has come to be a critical problem in view of the system performance. This is because the internal clock signal restricts operational frequency of the overall system in relation to the access time.
To meet the demand of higher internal clock signals, a delay lock loop (hereinafter referred to as DLL circuit) has been proposed as an internal clock signal generating circuit which receives an externally applied clock signal (external clock signal) and generates an internal clock signal which is in synchronization with the external clock signal.
In the following, a structure of the conventional DLL circuit will be described with reference to FIG.
17
.
The conventional DLL circuit
900
shown in
FIG. 17
includes a delay line
2
, a shift register
4
, a phase comparator
16
and a delay circuit
8
. DLL circuit
900
is a digital type DLL circuit which suppresses power supply noise more effectively than an analog type DLL circuit.
Delay line
2
delays an input external clock signal EXTCLK and outputs an internal clock signal INTCLK
1
. Delay circuit
8
delays internal clock signal INTCLK
1
by td2 and outputs the resulting signal (clock signal INTCLK
2
).
Phase comparator
16
compares phases of external clock signal EXTCLK and of clock signal INTCLK
2
output from delay circuit
8
. As a result of phase comparison, phase comparator
16
outputs an UP signal or a DOWN signal. Shift register
4
receives at its input the UP signal or the DOWN signal output from phase comparator
16
, and changes delay time of delay line
2
.
Structure of delay line
2
and a relation with shift register
4
will be described with reference to FIG.
18
.
Delay line
2
shown in
FIG. 18
includes a plurality of delay units U
0
, U
1
, . . . , Un, elements D
0
, D
1
, . . . , Dn and a plurality of NMOS transistors N
1
.
0
, N
1
.
1
, . . . , N
1
.n. In the following, delay units U
0
, U
1
, . . . , Un will be generally referred to as delay unit U, and elements D
0
, D
1
, . . . , Dn as element D.
Each delay unit U includes inverter circuits
40
and
41
. Elements D
0
, D
1
, . . . , Dn are connected to output nodes of corresponding delay units U
0
, U
1
, . . . , Un, respectively. NMOS transistors N
1
.
0
, N
1
.
1
, . . . , N
1
.n are connected between a signal line a
10
and corresponding elements D, respectively.
Delay unit U
0
receives a clock signal (in
FIG. 18
, IN). Over signal line a
10
, a signal (in
FIG. 18
, OUT) is output.
Shift register
4
includes a plurality of registers L
0
, L
1
, . . . , Ln. In the following, registers L
0
, L
1
, . . . , Ln will be generally referred to as register L.
Registers L
0
, L
1
, . . . , Ln are provided corresponding to NMOS transistors N
1
.
0
, N
1
.
1
, . . . , N
1
.n, respectively. NMOS transistors N
1
.
0
, N
1
.
1
, . . . , N
1
.n receive at respective gate electrodes, corresponding control signals d(
0
), d(
1
), . . . , d(n) from corresponding registers L.
Any one of the control signals d(
0
), d(
1
), . . . , d(n) output from shift register
4
is in an active state. In response to control signals d(
0
), d(
1
), . . . , d(n), the number of delay units U through which input signal IN is passed is determined.
The structure of shift register
4
will be described with reference to FIG.
19
.
As shown in
FIG. 19
, shift register
4
includes a plurality of registers L
0
, L
1
, L
3
, . . . , and a logic gate
47
.
Logic gate
47
receives at its input the DOWN signal and the UP signal output from phase comparator
16
, and outputs a signal T
0
. Registers L (except L
0
) each include an NAND circuit
43
, inverter circuits
44
,
45
and
46
, and NMOS transistors N
2
, N
3
and N
4
.
A first input node of each NAND circuit
43
receives a reset signal ZRST. Each NMOS transistor N
3
receives at its gate electrode the DOWN signal output from phase comparator
16
. Each NMOS transistor N
4
receives at its gate electrode the UP signal output from phase comparator
16
. Each NMOS transistor N
2
receives at its gate electrode the signal T
0
output from logic gate
47
.
Circuit structure of the register will be described, taking register L
2
as a representative example. NAND circuit
43
has a second input node connected to a node O
2
(connection node between register L
2
and register L
1
of the preceding stage).
Inverter circuit
44
is connected between a node O
2
and an output node of NAND circuit
43
. NMOS transistor N
2
is connected between inverter circuit
45
and NAND circuit
43
. Inverter circuit
46
is connected between an output node and an input node of inverter circuit
45
.
NMOS transistor N
3
is connected between a node O
3
(connection node between register L
2
and register L
3
of the succeeding stage) and inverter circuit
45
. NMOS transistor N
4
is connected between inverter circuit
45
and a node O
1
(connection node between registers L
0
and L
1
).
In shift register L
0
, an output node of NAND circuit
43
is connected to a node O
0
. Inverter circuit
44
is connected between node O
0
and the second input node of NAND circuit
43
. NMOS transistor N
2
is connected between inverter circuits
45
and
44
. It does not include NMOS transistor N
4
for receiving the UP signal.
Between a node O
0
and a ground potential GND, an NMOS transistor N
3
receiving the DOWN signal is arranged.
Control signals d(
0
), d(
1
), . . . are output from corresponding output nodes (input nodes of inverter circuit
46
) of respective inverter circuits
45
of registers L.
In the following, output signals from NAND circuits
43
in respective registers L
1
, L
2
, . . . will be represented as s(
1
), s(
2
), . . . , and the output signal from inverter circuit
44
in register L
0
will be represented as s(
0
).
The operation of shift register
4
will be described with reference to timing charts of
FIGS. 20A
to
20
L.
Referring to
FIGS. 20A
to
20
L, at time t0, reset signal ZRST is set to an L (low) level. Consequently, shift register
4
is set to an initial state. Signal d(
0
) is set to 1. A signal d(k) (where 1<k≦n) is set to 0.
Thereafter, reset signal ZRST is set to an H (high) level.
Thereafter, at time t1, when DOWN signal rises to the H level, a signal T
0
falls to the L level.
In response to control signal d(m), a signal s(m+1) (where 1≦m≦n−1) makes a transition. More specifically, upon reception of control signal d(
0
), signal s(
1
) goes from 1 to 0, as shown in
FIGS. 20F and 20G
.
Thereafter, at time t2, when DOWN signal falls to the L level, signal T
0
rises to the H level.
In response to signal s(m), control signal d(m) (where 0≦m≦n) changes. More specifically, in response to signal s(
0
), control signal d(
0
) changes from 1 to 0 as shown in
FIGS. 20E and 20F
.
In the similar manner thereafter, when DOWN signal rises to the H signal, signal s(m+1) changes in response to control signal d(m) (where 0≦m≦n−1) in synchronization with the rising edge of DOWN signal.
When DOWN signal falls to the L level, control signal d(i) changes in response to signal s(i) (where 0≦i≦n) in synchronization with the falling edge of DOWN signal.
More specifically, in synchronization with the rising edge of DOWN signal, state of the control signal is transferred in one direction (from d(m) to d(m+1)).
When UP signal rises to the H level, signal s(x−1) changes in response to control signal d(x) (where 1≦x≦n) in synchronization with the rising edge of UP signal.
When U
Iwamoto Hisashi
Sakamoto Wataru
Watanabe Naoya
Callahan Timothy P.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Minh
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