Internal clock generator for self-timed circuit with reduced dif

Details Internal clock generator for self-timed circuit with reduced dif Internal clock generator for self-timed circuit with reduced dif

1997-02-04

1999-05-25

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327294, H03K 300

Patent

active

059072563

ABSTRACT:
An internal clock generator is provided in which a clock having the smaller difference between the cycle of the clock and the delay time of a combinational circuit is generated. The combinational circuit included in a circuit to which the clock is supplied includes five signal processing portions which can become critical paths. Dummy signal processing portions are circuits corresponding to the signal processing portions, respectively. A clock which includes, in a cycle, the maximum value of the delays between the inputs and outputs of the dummy signal processing portions is generated. Consequently, if the critical path of a circuit for inputting the clock is changed and the delay time of the combinational circuit is increased or decreased, the cycle of the clock is increased or decreased accordingly. As a result, the difference between the cycle of the clock and the delay time of the combinational circuit is reduced so that the operation of the circuit is performed at higher speed.

REFERENCES:
patent: 4688947 (1987-08-01), Blaes et al.
patent: 5120988 (1992-06-01), Matsuki
patent: 5553276 (1996-09-01), Dean
patent: 5646554 (1997-07-01), Kim et al.
Technical Report of ICICE, ICD93-84, DSP93-45 (Sep. 1993); "Design of a Free-Running Multiplier", Yano et al. pp. 7-14.

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