Internal clock generator for a synchronous dynamic RAM

Details Internal clock generator for a synchronous dynamic RAM Internal clock generator for a synchronous dynamic RAM

1996-03-14

1998-04-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327291, H03K 513

Patent

active

057421943

ABSTRACT:
A first signal .phi.1 is produced from an external clock CLK. A second ond signal .phi.2 is produced from a clock enabling signal CKE for controlling an internal clock of a SDRAM. A phase compensated signal .phi.3 is produced by advancing the phase angle of the signal .phi.1. A control signal .phi.4 is produced by a D-type flipflop from the signals .phi.1 and .phi.2. A phase-advanced internal clock .phi.6 is produced from the signals .phi.3 and .phi.4 through an RS-type flipflop and an OR gate. The phase-advanced internal clock .phi.6 thus has no error producing waveform.

REFERENCES:
patent: 5396111 (1995-03-01), Frangioso et al.
Saeki et al., "SP 23.4: A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay", 1996 IEEE International Solid-State Circuits Conference, pp. 374-375.

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