Internal clock generating circuit for clock synchronous...

Details Internal clock generating circuit for clock synchronous... Internal clock generating circuit for clock synchronous...

1999-04-28

2003-10-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

C327S295000

Reexamination Certificate

active

06636110

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device and, more specifically, to a configuration for distributing an internal clock signal in a circuit device operating in synchronization with the clock signal. More specifically, the present invention relates to a configuration for distributing an internal clock signal in a clock synchronous semiconductor memory device in which taking of an external signal and data and output of data are performed in synchronization with an externally applied clock signal.
2. Description of the Background Art
FIG. 32
schematically represents an overall configuration of a convention al clock synchronous semiconductor memory device. Referring to
FIG. 32
, the clock synchronous semiconductor memory device includes a memory array
900
having a plurality of memory cells arranged in a matrix of rows and columns; a synchronizing circuit
902
receiving an externally applied clock signal EXCLK and generating an internal clock signal INCLK synchronized with the external clock signal EXCLK; an address input circuit
904
taking in an externally applied address signal AD in synchronization with the internal clock signal INCLK from synchronizing circuit
902
and generating an internal address signal; a control signal input circuit
906
taking an external command &PHgr;C in synchronization with the internal clock signal INCLK and generating an internal control signal; a control circuit
908
generating various control signals necessary for a designated operation mode in accordance with the internal control signal from control signal input circuit
906
; a cell selecting circuit
910
operating under the control of control circuit
908
, and selecting a memory cell in memory cell array
900
in accordance with the internal address signal applied from address input circuit
904
; and a data input/output circuit
912
operating under the control of control circuit
908
and performing data input/output to and from the memory cell selected by cell selecting circuit
910
in synchronization with internal clock signal INCLK.
The command signal &phgr;C includes a plurality of external control signals such as a row address strobe signal ZRAS, a column address strobe signal and a write enable signal ZWE, and by a combination of states of the plurality of external control signals at a rising edge of the internal clock signal INCLK, a command designating an operation mode is formed.
FIG. 33
is a timing chart representing an operation of the clock synchronous semiconductor memory device shown in FIG.
32
. In the following, the operation of the clock synchronous semiconductor memory device shown in
FIG. 32
will be described with reference to FIG.
33
.
In a cycle preceding a cycle #a of external clock signal EXCLK, an active command is applied and in memory array
900
, memory cells corresponding to an addressed row are driven to and held at a selected state.
In the clock cycle #a, the command signal &phgr;C is set to a prescribed state, and a write command designating a data write is applied. In the clock cycle #a, in synchronization with a rise of external clock signal EXCLK, address input circuit
904
takes in the external address signal AD and generates an internal address signal. Data input/output circuit
912
takes in externally applied write data d
0
in synchronization with the external clock signal EXCLK in accordance with the write command. Cell selecting circuit
910
selects a memory cell in accordance with the address signal applied from address input circuit
904
.
In successive clock cycles starting at clock cycle #a, write data d
1
, d
2
and d
3
are taken in, respectively in synchronization with the rise of the external clock signal EXCLK. The write data d
0
to d
3
are written to memory cells selected by the cell selecting circuit
910
of memory array
900
in a prescribed sequence. The number of data written or read successively when a command is applied is referred to as a burst length.
FIG. 33
represents an example of a data writing operation when the burst length is
4
.
In a cycle #b of external clock signal EXCLK, the command signal &phgr;C is set to a prescribed state and a read command designating a data read is applied. In accordance with the read command, address input circuit
904
takes in an external address signal AD in synchronization with a rise of external clock signal EXCLK and generates an internal address signal. Cell selecting circuit
910
selects an addressed memory cell of memory array
900
, and data of the selected memory cell is applied to data input/output circuit
912
. A certain time period is necessary from the selection of the memory cell by cell selecting circuit
910
until transfer of data of the selected memory cell to data input/output
912
. In a cycle preceding the cycle #c of external clock signal EXCLK, valid data is output from data input/output circuit
912
, the read data q
0
is established at a rising edge of external clock signal EXCLK in the clock cycle #c and sampled by an external device. Thereafter, data of the burst length are read in synchronization with the external clock signal EXCLK successively. The clock cycle period from clock cycle #b to clock cycle #c is generally referred to as CAS latency, and
FIG. 33
represents an example of a reading operation where CAS latency is 3.
In a clock synchronous semiconductor memory device such as the one shown in
FIG. 32
, the external address signal and the command signal are taken in synchronization with external clock signal EXCLK (internal clock signal INCLK). Therefore, it is unnecessary to consider any skew between control signals, and a timing of starting an operation of the internal circuit can be made advanced, enabling high speed access.
Further, since data input/output is also in synchronization with the external clock signal EXCLK, data transfer rate is effectively the same as the rate of the external clock signal EXCLK, and therefore high speed data transfer is realized.
Synchronizing circuit
902
generates the internal clock signal INCLK which is synchronous with the externally applied clock signal EXCLK, and determines the timing of taking signals of address input circuit
904
and control signal input circuit
906
. Therefore, in address input circuit
904
and control signal input circuit
906
, taking of accurate external signals and generation of internal signals at a faster timing are possible. Further, in data input/output circuit
912
, it is possible to input/output data in accordance with the external clock signal EXCLK, and therefore accurate data input/output and high speed data transfer can be realized.
FIG. 34A
represents a schematic configuration of the synchronizing circuit shown in FIG.
32
. Synchronizing circuit
902
shown in
FIG. 34A
is formed by a synchronizing circuit having a feed back loop such as a phase locked loop (PLL). Synchronizing circuit
902
adjusts phase of the internal clock signal INCLK such that the externally applied external clock signal EXCLK and the internal clock signal INCLK come to have the same phase. Therefore, as can be seen from
FIG. 34B
, the internal clock signal INCLK is in phase with the external clock signal EXCLK.
The external control signal and the address signal are generated with the external clock signal EXCLK being a reference. Therefore, in the semiconductor memory device, the command signal &phgr;C has extremely small skew with respect to the external clock signal EXCLK (with the direction of signal transfer being the same), and therefore sufficient set up time Ts and sufficient hold time Th are ensured. It should be noted, however, that though synchronizing circuit
902
has a function of making the phase of internal clock signal INCLK matched with external clock signal EXCLK, synchronizing circuit
902
does not have a function of adjusting skew generated n the internal clock signal INCLK is transmitted inside the semiconductor memory device.
FIG. 35A
schema

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