Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-03-04
2001-03-27
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S390000
Reexamination Certificate
active
06208197
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit charge pumps and, more particularly, to integrated circuit charge pumps with circuits to limit the voltage at nodes internal to the charge pump.
BACKGROUND INFORMATION
Some integrated circuits (i.e., chips) require supply voltages of different levels, which may be generated “on-chip” using voltage generators incorporated into the chip. For on-chip generated supply voltages that are higher than the externally supplied voltage or voltages, charge pumps are typically used as the voltage generator.
FIG. 1
is a block diagram illustrative of a conventional integrated circuit charge pump
10
used to generate a supply voltage V
H
having a level that is higher than the level of the externally provided supply voltage. Charge pump
10
includes a main pump stage (WPS)
11
, a well pump stage (WPS)
13
, and two P-channel transistor P
14
and P
15
serving as pass gates. MPS
11
and WPS
13
are each connected to a VDD supply bus and a ground bus to receive power from an external power source (not shown) providing supply voltage VDD. In addition, MPS
11
and WPS
13
are connected to receive “n” (n representing an integer greater than zero) pump control signals through a control line
16
. The output leads of MPS
11
and WPS
13
are connected to the sources of P-channel transistors P
14
and
15
, respectively.
P-channel transistors P
14
and P
15
have their gates connected to a line
18
to receive a pump boost control signal PMPBST. When asserted (i.e., a logic low level in this embodiment), signal PMPBST has a boosted level (i.e., a level that is higher than the normal VDD level) and is used to control charge transfer from the output leads of MPS
11
and WPS
13
.
The drain of P-channel transistor P
14
is connected to output lead
19
, whereas the drain of P-channel transistor P
15
is connected to the well of P-channel transistor P
14
. In this example, P-channel transistor P
14
is implemented in an N-well. As is well known in the art of semiconductor devices, the well must be maintained at a potential (i.e., V
WELL
) that is equal to or greater than the highest potential at either the source or the drain of P-channel transistor P
14
for proper transistor operation. However, due to fluctuations in load current, the level of voltage V
H
at output lead
19
(i.e. the drain of P-channel transistor P
14
) will at times be greater than the level of the voltage at output lead of MPS
11
(i.e., the source of P-channel transistor P
14
). In addition, the voltage level at the source of transistor P
14
at times is greater than the level of voltage V
H
. Thus, simply tying the well to the source or the drain of P-channel transistor P
14
would not be effective.
To address this issue, charge pump
10
uses WPS
13
to maintain the level of voltage V
WELL
at a predetermined level that is higher than the maximum voltage levels of the source and drain of P-channel transistor
14
. Those skilled in the art will appreciate that the capacitance and leakage of the well of P-channel transistor P
15
is typically relatively small and, thus, the voltage level at the source of P-channel transistor P
15
will generally always be greater or equal to the voltage level of the well. Consequently, tying the drain of P-channel transistor P
15
to the well is effective in maintaining the voltage level of the well at or above the voltage levels at the source and drains of P-channel transistor P
15
.
To maintain supply voltage V
H
at the desired level, a control circuit (not shown) conventionally provides the pump control signals on line
16
so as to cause MPS
11
and WPS
13
to transfer charge to the sources of P-channel transistors P
14
and P
15
, respectively. Pump boost signal PMPBST is used to control the state of P-channel transistors P
14
and P
15
to transfer charge from MPS
11
and WPS
13
to output lead
19
and to the well of P-channel transistor
14
, respectively. More specifically, P-channel transistors P
14
and P
15
are turned off when MPS
11
and WPS
13
are charging their pumping capacitors, which are connected to the sources of P-channel transistors P
14
and P
15
, respectively. In particular, MPS
11
and WPS
13
boost the voltage at their respective output leads to a level significantly greater than the level of the external supply voltage. This boosting is typically achieved by charging a capacitor in the pump stage so that a first lead is at the ground potential while the second lead is at the external supply voltage level. Then the pump stage increases the voltage level at the first lead, thereby boosting, at least initially, the voltage at the second lead to a level higher than the external supply voltage level.
As MPS
11
and WPS
13
have boosted the voltage level at the sources of P-channel transistors P
14
and P
15
, signal PMPBST is provided so as to turn on P-channel transistors P
14
and P
15
, thereby allowing charge to redistribute from the pumping capacitors of MPS
11
and WPS
13
, to the sources of P-channel transistors P
14
and P
15
, and to output lead
19
and the well of P-channel transistor P
14
, respectively. In this way, charge pump
10
generates supply voltage V
H
and maintains the level of voltage V
WELL
so as to be equal to or higher than the levels of the voltages at the source and drain of P-channel transistor P
14
.
However, if the voltage level at the well of P-channel transistor P
14
gets too high, the risk of junction breakdown in devices connected to the well is increased. This problem can be exacerbated during burn-in testing during which the external supply voltage is increased to a level that is higher than the normal operational level. Accordingly, there is a need for a charge pump that can limit the voltage at nodes internal to the charge pump.
SUMMARY
In accordance with the present invention, a charge pump is provided that limits the voltages at nodes internal to the charge pump. This feature can be advantageously used to reduce the risk of junction breakdown in the charge pump. One embodiment of the present invention includes a first pump circuit, a second pump circuit, a first clamping circuit and a second clamping circuit. In one aspect of the present invention, the first clamping circuit is used to limit the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. In another aspect of the present invention, the voltage level at a first node from which charge is redistributed to the well is limited by the second clamping circuit that is configured to provide a conductive path from the first node to the output lead when the voltage level of the first node reaches a second predetermined limit. Limiting the voltage levels at the well and the first node reduces the risk of junction breakdown of devices connected to the well.
In another embodiment of the present invention, the charge pump includes a pump circuit having a logic circuit and a capacitor pump circuit. In one aspect of the present invention, the logic circuit is configured, depending on the level of an external supply voltage, to vary the rate at which a capacitor node in the capacitor pump circuit is boosted. This aspect of the present invention can be advantageously used to reduce the rate at which the capacitor node can be boosted when the external supply voltage is relatively high, thereby reducing the risk of junction breakdown. In a further aspect of the present invention, in addition to varying the rate at which the capacitor node is boosted, the voltage difference between the capacitor node and the external supply voltage is varied as a function of the level of the external supply voltage. This aspect of the present invention can be advantageously used decrease the voltage level at the capacitor node relative to the level of the external supply voltage when the level of the external supply voltage is relatively high, thereby providing another mechanism to reduce the risk of junct
Stephens, Jr. Michael C.
Ternullo, Jr. Luigi
Cunningham Terry D.
Huang Jiawei
Patents J. C.
Tra Quan
Vanguard International Semiconductor Corp.
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