Internal bus architecture employing a simplified rapidly executa

Details Internal bus architecture employing a simplified rapidly executa Internal bus architecture employing a simplified rapidly executa

1983-12-29

1990-08-07

Clark, David L.

Boots, shoes, and leggings

G06F 1338

Patent

active

049473166

ABSTRACT:
An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were architected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.

REFERENCES:
patent: 3753234 (1973-08-01), Gilbert et al.
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4467412 (1984-08-01), Hoff
patent: 4493020 (1985-01-01), Kim et al.
patent: 4494188 (1985-01-01), Nakane et al.
patent: 4530051 (1985-07-01), Johnson et al.
patent: 4564901 (1986-01-01), Tomlinson et al.
patent: 4594660 (1986-06-01), Guenthner et al.
patent: 4638453 (1987-01-01), Gran et al.
Summers, R. C. and Wood, C., "Message Based Protocol for Interprocessor Communication", IBM TDB, Dec. 1979, pp. 2893-2895.

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