Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2000-04-18
2004-03-09
Corrielus, Jean B. (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C370S503000, C327S144000, C375S316000
Reexamination Certificate
active
06704379
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to intermittent receiving systems and, more particularly, to intermittent receiving systems which can be used as mobile communication terminal with reduced power consumption.
Mobile communication terminals of PHS (Personal Handy-Phone System), PDC (Personal Digital Cellular) system, etc. are popularly used. The mobile communication terminal is required to be operable for a long time when it is charged once. The intermittent reception is known as a receiving method for reducing power consumption during a waiting operation, which occupies a majority of the operating time.
In the PDC system, a frame synchronization symbol is provided in a central part of a transmission signal. Therefore, it is necessary to maintain a reception clock even during the non-receiving time or adopt a reception clock reproducing system, which is high in level with respect to the leading part of the transmission signal. In the former case, the power consumption is increased. In the latter case, the circuit construction is greatly complicated. In addition, the reliability of the demodulating process is deteriorated.
In the PHS system, the bit synchronization signal is sufficiently provided in the first half of the transmission signal. It is thus possible to adopt a simplified reception clock reproducing system. On the downside side, however, an excessively long receiving process time is required.
As prior art pertaining to the present invention, Japanese Patent Laid-Open No. 10-117164 and Japanese Patent Laid-Open No. 9-321687 disclose means for intermittently on-off operating the power supply of a receiving part. Also, Japanese Patent Laid-Open No. 9-153854 discloses a system, which includes high- and low-rate clock oscillators for generating a high- and a low-rate clock, respectively. In this system, during a waiting time the internal circuit executes an operation under control of the low-rate clock, thus reducing the power consumption.
The intermittent receiving system is required to suppress current consumption during a non-receiving time section for reducing the current consumption in an intermittent receiving operation, operate the receiving system circuit for a time which is as close to a time section with a desired received signal present therein as possible and ensure freedom from receiving performance deterioration.
Where the high- and low-rate clocks are used in a switching fashion, a demodulation clock used in the receiving system circuit should be accurately timed to the received signal arrival timing. In the prior art intermittent reception, therefore, stable operation of the high-rate clock oscillator is necessary at the time of the demodulation clock rise.
When the high-rate clock oscillator rise timing is earlier than the demodulation clock oscillator rise timing, extra power is consumed. On the other hand, when the high-rate clock oscillator rise timing is later than the demodulation clock oscillator rise timing, erroneous reception is likely.
In view of the above background, an intermittent receiving system capable of reducing power consumption in the intermittent receiving process, is desired. In addition, an intermittent receiving system is desired, in which the reduction of the power consumption is realized in connection with the process in the intermittent receiving operation and the process prior thereto, is desired.
Furthermore, an intermittent receiving system is desired, in which the process in the intermittent receiving operation is realized such that the high-rate clock oscillator rise operation is substantially synchronized to the demodulation clock oscillator rise operation.
Still further, an intermittent receiving system is desired, in which the above substantial synchronizing process is executed according to a value obtained by calculation which is executed before the intermittent receiving operation.
Yet further, an intermittent receiving system is desired, in which the next signal receiving timing can be estimated according to the counts of pulses of the high- and low-rate clocks.
Further, an intermittent receiving system is desired, in which the operation of the high-rate clock oscillator is executed in response to the operation of the demodulation clock oscillator according to a predicted receiving timing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an intermittent receiving system capable of reducing power consumption in the intermittent receiving process.
Another object of the present invention is to provide an intermittent receiving system, in which the reduction of the power consumption is realized in connection with the process in the intermittent operation and the process prior thereto.
A further object of the present invention is to provide an intermittent receiving system, in which the process in the intermittent receiving operation is realized such that the high-rate clock oscillator rise operation is substantially synchronized to the demodulation clock oscillator rise operation.
A still further object of the present invention is to provide an intermittent receiving system, in which the above substantial synchronizing process is executed according to a value obtained by calculation which is executed before the intermittent receiving operation.
A yet further object of the present invention is to provide an intermittent receiving system, in which the next signal receiving timing can be estimated according to the counts of pulses of the high- and low-rate clocks.
A further object of the present invention is to provide an intermittent receiving system, in which the operation of the high-rate clock oscillator is executed in response to the operation of the demodulation clock oscillator according to a predetermined receiving timing.
According to an aspect of the present invention, there is provided an intermittent receiving system comprising: a demodulating unit for executing a demodulating process on a received radio signal, the demodulating unit generating a demodulation clock in the demodulating process; a first clock generating unit for generating a high-rate clock compared to the demodulation clock; a second clock generating unit for generating a low-rate clock compared to the demodulation clock; and a timing control unit for estimating the timing of rise of the demodulation clock corresponding to the next reception timing in intermittent reception and controlling the first clock unit substantially in synchronism to the demodulation clock rise timing.
The timing control unit calculates the intermittent receiving interval according to the counts of pulses of the high- and low-rate clocks.
The timing control unit determines the intermittent receiving interval by calculating the interval of a particular instant signal contained in the received radio signal according to the counts of pulses of the high- and low-rate clocks.
When the particular instant signal is not present at the leading part of the received signal, the timing control calculates the relation between the forefront instants leading portion of the particular instant signal and the received radio signal according to the counts-of pulses of the low- and high-rate clocks and synchronizes the demodulation clock to the forefront instant leading part of received signal by shifting the demodulation clock generation timing according to calculated counts.
The timing control unit causes the operation of the first clock generating unit to be started before the demodulation clock generation timing.
According to another aspect of the present invention, there is provided an intermittent receiving method comprising: a step of generating a demodulation clock; a step of executing a demodulating process on a received radio signal; a step of generating a high-rate clock at a high rate compared to the demodulation clock; a step for generating a low-rate clock at a low rate compared to the demodulation clock; a step of estimating the timing of rise of the demodulation clock corresponding to the next reception timing in intermittent re
Corrielus Jean B.
Dickstein Shapiro Morin & Oshinsky LLP.
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