Intermittent oscillation circuit

Details Intermittent oscillation circuit Intermittent oscillation circuit

2002-05-28

2004-05-04

Callahan, Timothy P. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

C331S100000

Reexamination Certificate

active

06731177

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an intermittent oscillation circuit, and more particularly relates to an intermittent oscillation circuit utilized in a RF transmitting/receiving system. By controlling the duty cycle of an oscillatory signal outputted from the intermittent oscillation circuit, data collision can be decreased while data is transmitted or received, and meanwhile the power consumption can be decreased.
BACKGROUND OF THE INVENTION
Among many communication products, oscillators or oscillation circuits have been widely utilized, wherein a simple oscillation circuit can be constructed by many inverters connected in series. Please referring to
FIG. 1
,
FIG. 1
is a diagram showing a conventional oscillation circuit. As shown in
FIG. 1
, an oscillation circuit
10
is constructed by certain number of inverters
15
connected in series, and the output terminal
25
of the oscillation circuit
10
is electrically connected to the input terminal
20
of the oscillation circuit
10
for feedbacking an output signal to the input terminal
20
, so that oscillatory signals can be continuously outputted from the oscillation circuit
10
. Please referring to
FIG. 2
,
FIG. 2
is a diagram showing the wave form outputted from the oscillation circuit shown in FIG.
1
.
About the construction and operation theorem of inverter
15
, please refer to FIG.
3
and the following description.
FIG. 3
is a diagram showing a conventional inverter constructed by a PMOS and a NMOS. The conventional inverter
15
constructed by a PMOS
30
and a NMOS
35
is shown in
FIG. 3
, wherein the drain
40
of the PMOS
30
is electrically connected to an operation voltage
75
, and the source
60
of the NMOS
35
is electrically connected to a ground
70
, and the gate
50
of the PMOS
30
and the gate
65
of the NMOS
35
are electrically connected to an input terminal
80
of the inverter
15
, and the source
45
of the PMOS
30
and the drain
55
of the NMOS
35
are electrically connected to an output terminal
85
of the inverter
15
.
If an input signal is implemented at the input terminal
80
of the inverter
15
, and the voltage level (V
1
) of the input signal is equal to or smaller than the threshold voltage of the PMOS
30
(i.e. V
1
≦V
t1
), then the PMOS
30
is activated, but the NMOS
35
is not activated, so that the current from the operation voltage
75
will flow to the output terminal
85
through the PMOS
30
, such as shown by the current direction
90
in FIG.
3
. Therefore, the inverter
15
outputs a signal with a high voltage level (or called “1” logic signal).
Additionally, if an input signal is implemented at the input terminal
80
of the inverter
15
, and the voltage level (V
1
) of the input signal is equal to or larger than the threshold voltage of the PMOS
30
(i.e. V
1
≧V
t1
), then the NMOS
35
is activated, but the PMOS
30
is not activated, so that the current from the operation voltage
75
can not flow to the output terminal
85
through the PMOS
30
, i.e. the current can flow in the direction as shown by the current direction
90
in FIG.
3
. Instead, the current from the input terminal will flow to the ground
70
through the NMOS
35
, such as shown by the current direction
95
in FIG.
3
. Therefore, the inverter
15
outputs a signal with low voltage level (or called “0” logic signal), therefore completing the inversion process in the inverter
15
.
In the conventional RF transmitting/receiving system, the conventional oscillation circuit
10
shown in
FIG. 1
is usually utilized in transmitting modules, such as cards or tags, for generating oscillatory signals by which the data saved in the transmitting modules is transmitted by RF to the receiving terminal of the conventional RF transmitting/receiving system. However, if the same oscillation circuit is applied to each of numerous transmitting modules, serious data collisions will happen while those numerous transmitting modules transmit data to the conventional RF transmitting/receiving system at the same time, causing the conventional RF transmitting/receiving system failing to accurately receive the data from each of the transmitting modules, or causing the delay of the data in receiving process, so that the performance and accuracy of data transmission are decreased.
SUMMARY OF THE INVENTION
In view of the background of the invention described above, in the conventional RF transmitting/receiving system, the conventional oscillation circuit utilized in transmitting modules just only generates an oscillatory signal having a fixed duty cycle. While numerous transmitting modules perform data transmission simultaneously, data collision occurs in transmission channels, so that the conventional RF transmitting/receiving can not receive the data from each of the transmitting modules accurately.
It is the principal object of the present invention to provide an intermittent oscillation circuit utilized in a RF transmitting/receiving system, wherein the intermittent oscillation circuit has a function of controlling the duty cycle of outputted oscillatory signal. Therefore, thereby improving the data collision occurring while numerous transmitting modules perform data transmission at the same time, also lowering the power consumption.
In accordance with the aforementioned object of the present invention, the present invention provides an intermittent oscillation circuit comprising: a power supply circuit comprising a current source and a first resistor, wherein one terminal of the current source and one terminal of the first resistor both are electrically connected to ground, and the other terminal of the current source and the other terminal of the first resistor both are electrically connected to an output terminal of the power supply circuit; a power control circuit comprising: a second resistor, a first PMOS and a comparing module, wherein one terminal of the second resistor is electrically connected to the output terminal of the power supply circuit, and the drain of the first PMOS is electrically connected to the other terminal of the second resistor, and the source of the first PMOS is electrically connected to the ground, and the gate of the first PMOS is electrically connected to the output terminal of the comparing module; an inversion circuit comprising: a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and at least one inverter, wherein one terminal of the third resistor, one terminal of the fourth resistor and one terminal of the fifth resistor all are electrically connected to the output terminal of the comparing module, and one terminal of the first capacitor and one terminal of the second capacitor both are electrically connected to the ground, and the other terminal of the second capacitor is electrically connected to the other terminal of the fourth resistor, and the at least one inverter is constructed by a second PMOS and a NMOS, and the source of the NMOS is electrically connected to the ground, and the drain of the second PMOS is electrically connected to the output terminal of the power supply circuit, and the gate of the second PMOS and the gate of the NMOS both are electrically connected to the other terminal of the first capacitor and the other terminal of the fifth resistor, and the source of the second PMOS and the drain of the NMOS both are electrically connected to the other terminal of the third resistor and used as an output terminal of the intermittent oscillation circuit.


REFERENCES:
patent: 4328570 (1982-05-01), Nakagawa
patent: 5907600 (1999-05-01), Fuller et al.
patent: 6025757 (2000-02-01), Tsukagoshi et al.
patent: 6552623 (2003-04-01), Nishida et al.

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