Intermittenceless switching system

Details Intermittenceless switching system Intermittenceless switching system

1992-05-29

1994-10-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 953, H04Q 1104

Patent

active

053532813

ABSTRACT:
An intermittenceless switching system includes two speech path memories having sufficient capacity to store a single frame of data having a plurality of time slots. The incoming data is stored in one memory, while the outgoing data is read from the other memory. A control circuit continuously alternates the read/write functions between the two memories. A control memory is used to store switch control information. The system includes a buffer memory that is present between a data processor and the control memory to prevent switch operation during data transmission. The system also includes a monitoring circuit for detecting an indication bit signifying the presence or absence of data in the time slot.

REFERENCES:
patent: 4597079 (1986-06-01), Aoki et al.
patent: 4941141 (1990-07-01), Hayano
patent: 5040174 (1991-08-01), Takeuchi et al.
patent: 5042082 (1991-08-01), Dahlin

Affiliated with

Also associated with

Rating

Intermittenceless switching system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Intermittenceless switching system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Intermittenceless switching system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-586865