Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1997-11-19
1999-10-12
Kelley, Nathan K.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257758, H01L 2348
Patent
active
059659408
ABSTRACT:
A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an intermetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.
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Kelley Nathan K.
Micro)n Technology, Inc.
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