Intermediate voltage generating circuit and nonvolatile semicond

Details Intermediate voltage generating circuit and nonvolatile semicond Intermediate voltage generating circuit and nonvolatile semicond

1997-06-24

1999-03-02

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518909, 36518518, 365207, G11C 1606

Patent

active

058779850

ABSTRACT:
A pull-up P-channel MOS transistor is connected between an output node and a VPP power supply terminal, while a pull-down N-channel MOS transistor is connected between the output node and a VSS power supply terminal. The output node has been electrically charged to VPP in an initial state. When a control signal SAEN has been made to be the "L" level, the change in the output node is gradually discharged. Since the output from the differential amplifying circuit is at the "H" level, the voltage at the output node is rapidly lowered. When the voltage at the output node has been made to be lower than a predetermined level, output voltage VOUT having a predetermined level is output.

REFERENCES:
patent: 5253201 (1993-10-01), Atsumi et al.
patent: 5673232 (1997-09-01), Furutami
patent: 5689460 (1997-11-01), Ooishi

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