Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1994-09-12
1995-05-30
Limanek, Robert P.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257647, H01L 2712
Patent
active
054204534
ABSTRACT:
A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.
REFERENCES:
patent: 4755477 (1988-07-01), Chao
patent: 5159428 (1992-10-01), Rao et al.
De La Moneda, IBM Tech. Disclosure Bulletin, vol. 25, No. 11B, Apr. 1983, pp. 6131-6142.
Bryant Frank R.
Chen Fusen E.
Hodges Robert L.
Hill Kenneth C.
Jorgenson Lisa K.
Limanek Robert P.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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