Intermediate potential generation circuit

Details Intermediate potential generation circuit Intermediate potential generation circuit

1995-08-30

1998-03-31

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327540, 327543, 327546, 323313, G05F 110

Patent

active

057342920

ABSTRACT:
The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.

REFERENCES:
patent: 4117353 (1978-09-01), Butler et al.
patent: 4663584 (1987-05-01), Okada et al.
patent: 4812735 (1989-03-01), Sawada et al.
patent: 4906914 (1990-03-01), Ohsawa
patent: 5305259 (1994-04-01), Kim
patent: 5369354 (1994-11-01), Mori
patent: 5436552 (1995-07-01), Kajimoto
patent: 5532578 (1996-07-01), Lee
patent: 5534817 (1996-07-01), Suzuki et al.

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