Intermediate instruction execution processor which resolves...

Details Intermediate instruction execution processor which resolves... Intermediate instruction execution processor which resolves...

1998-01-09

2002-05-07

Vu, Viet D. (Department: 2758)

Reexamination Certificate

active

06382846

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to processor design. In particular, the present invention pertains to a processor capable of executing instructions containing symbolic references (operands specified as symbols, rather than as “numeric references” or run-time executable functions that evaluate to specific memory locations or “slots”) that are dynamically resolved to numeric references during execution.
BACKGROUND OF THE INVENTION
A pipelined processor is a processor having several sequentially connected stages or sections. For example, a processor can have an instruction cache, an instruction decoder, a register read stage, an execution stage and a post-execution register write stage. The instruction cache is a memory for storing instructions pending execution. Because of the temporal locality of reference (tendency to repeat execution of a recently executed instruction) and spatial locality of reference (tendency to execute instructions in memory locations nearby the memory locations of a recently executed instruction) properties of instruction execution, the instruction cache reduces the number of accesses to a slower main memory, thereby increasing instruction execution speed. The instruction decoder decodes the instruction into control signals for selecting/retrieving the appropriate operands and arithmetic, logic or memory access operations on such operands. The register read stage may be provided in certain processors having a register file for quickly and efficiently retrieving information contained in, or indexed by, registers of the register file. The execution stage illustratively includes one or more functional units or sections for executing the operation on the operands as specified in the decoded instruction. The post execution register write stage is for quickly and efficiently storing values in the register file. Other stages or configurations are also known in the prior art.
In addition to the above noted stages, a data cache is also often provided in the processor. Like the instruction cache, the data cache stores data, e.g., different operands, pending execution thereon. The data cache is separated from the instruction cache because the temporal and spatial locality of reference properties of operands are typically independent of those of instructions.
Several architectures are known for connecting the instruction and data caches to the other stages of the processor, such as shown in
FIGS. 1-3
.
FIG. 1
shows an architecture which is similar to that employed in a processor manufactured by MIPS™. An instruction cache
12
and a separate data cache
14
feed the other stages
10
in parallel. Either cache
12
or
14
can access the bus interface
16
so as to receive information (e.g., instructions or data) from, or transmit information to, devices outside the processor, such as the processor bus, L
2
cache, main memory, etc. The architecture of
FIG. 1
is characterized as conserving manufacturing costs and integrated circuit chip space and also improving execution speed as a result of separating the instruction cache
12
from the data cache
14
.
A shortcoming of the architecture of
FIG. 1
is its inability to support instruction code self-modification. That is, instructions executing in stages
10
cannot modify instructions that reside in the instruction cache
12
. The reason is as follows. Consider that both the data cache
14
and the instruction cache
12
stores facsimile copies of instructions and data of a main memory. If another device requests to access the same data or instructions for which the instruction cache
12
or data cache
14
has a copy, the instruction cache
12
or data cache
14
must relinquish control of (i.e., invalidate or erase) such instructions or data. Furthermore, if the copy of such instruction or data in the instruction cache
12
or data cache
14
has been modified since it was retrieved from the main memory, such modifications must be written back to the main memory. Since the same data or instructions may be modified repeatedly, the instruction cache
12
and data cache
14
preferably defer writing back modified instructions or data until another device requests such instructions or data; until the instruction cache
12
or data cache
14
runs out of storage space; or as a result of a specific program instruction to do so. (This manner of deferring updates of modifications to information is referred to as a “write back”, policy or scheme). The problem is that all modified information, whether such modified information is program data or executable instructions, is outputted to the data cache
14
. Thus, it is possible that the following scenario can occur: the instruction cache
12
writes back a copy of a to-be-modified instruction shortly after submitting the instruction that modifies it to the other stages
10
for execution. The modified instruction is written to the data cache
14
. Before the data cache
14
writes back the modified instruction, the instruction cache
12
reads in the same instruction for execution. However, because the instruction cache
12
has no way of knowing that the data cache
14
possesses a modified version of the instruction (indeed the data cache
14
does not even know this), the instruction cache
12
obtains the stale unmodified copy of the instruction from the main memory. This result is a serious violation of the memory coherency restriction imposed on all caches
12
and
14
because the program would not execute as specified in the program instructions, possibly causing an unrecoverable system error or crash.
FIG. 2
shows a second architecture similar to that employed in Intel's™'486™ processor. Unlike the architecture of
FIG. 1
, a single unified cache
18
is provided for storing instructions and data. As a result, the performance of this processor architecture is lower than that of the processor shown in FIG.
1
. Nevertheless, this architecture is inexpensive and can support self-modifying instructions.
FIG. 3
shows a third architecture similar to that employed in Intel's™ Pentium™ processor. The instruction cache
20
is modified to include a snoop circuit
22
. The snoop circuit
22
keeps track of the modifications to data loaded into the data cache
14
, including modifications to instructions. As such, in the above scenario, if the instruction cache
20
attempted to load a modified instruction prior to the data cache
14
writing back the modifications, the snoop circuit
22
would obtain the modified copy of the instruction from the data cache
14
, not the stale copy from the main memory. Thus, the architecture of
FIG. 3
has a fast execution speed and accommodates self-modifying instructions. The problem is that the complexity of the snoop circuit
22
far increases the cost of the architecture of FIG.
3
. The increase in cost might not be justifiable for low cost processors used in certain applications.
Executable instructions are traditionally generated one of two ways: by compiling source code instructions or interpreting source code instructions. In compiling source code, a compiler program reads each textual source code instruction. In response to each instruction, the compiler generates one or more machine executable instructions (“object code” instructions). The source code instructions specify high-level functions applied to variables in human readable form. Source code instructions are often specified as functions performed on variables in symbolic form as it is easier for a human to distinguish variables identified by symbols rather than memory locations. For example, the source code instruction “i:=i+2;” specifies that the variable identified the symbol i is to be incremented by 2. A later instruction “i:=i/2;”, specifies that the same variable identified by the symbol i should be divided by 2. The compiler not only translates each function to one or more operations to be performed on variables, but furthermore assigns memory locations or slots to each variable and replaces the symboli

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