Intermediate decimal correction for sequential addition

Details Intermediate decimal correction for sequential addition Intermediate decimal correction for sequential addition

1985-06-28

1988-01-05

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

047180331

ABSTRACT:
Apparatus is provided to restore an excess six correct to every digit of an intermediate result which did overflow during the previous addition operation during a sequence of repeated BCD addition operations. A carry register is defined to store and feedback logical signals indicative of the occurance of an overflow event.

REFERENCES:
patent: 3958112 (1976-05-01), Miller
patent: 4041290 (1977-08-01), Fressineau et al.
patent: 4197587 (1980-04-01), Stettmaier et al.
Guyton, "Simplifying Sum-Correction Logic for Adding two BCD Numbers", Electronics, vol. 47, No. 11, p. 108, May 30, 1974.

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