Static information storage and retrieval – Powering
Reexamination Certificate
2001-08-22
2003-05-27
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C365S189090
Reexamination Certificate
active
06570807
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention is directed to voltage pumps and, more particularly, to voltage pumps and methods of operating voltage pumps used in memory devices.
2. Description of the Background
Pump circuits are commonly used to create voltages that are more positive or more negative than available supply voltages. Two types of voltage pumps that are commonly used in memory devices, such as Dynamic Random Access Memories (DRAM), are a Vcc pump which generates a boosted word line voltage and a Vbb pump which generates a negative substrate bias voltage. The Vcc pump is built primarily from nMos transistors while the Vbb pump is built from pMos transistors.
The operation of a voltage pump will now be explained with reference to a simple voltage pump circuit illustrated in FIG.
1
. For this positive voltage pump circuit, consider that for one phase of a pump cycle the clock signal CLK is high. During this phase, node A is at ground potential and node B is clamped to source voltage Vcc minus Vth, which is the voltage drop across transistor M
1
. The charge stored in capacitor C
1
is given by the following equation:
Q
1
=
C
1
(
Vcc−Vth
)coulombs
During the second phase, the clock CLK will transition low, which brings node A high. As node A rises to the source voltage Vcc, node B begins to rise above Vcc minus Vth, shutting off transistor M
1
. At the same time, as node B rises one Vth above Vload, transistor M
2
begins to conduct. The charge from capacitor C
1
is transferred through transistor M
2
and shared with capacitor Cload. That action effectively pumps charge into the capacitor Cload and ultimately raises the output voltage Vout. During subsequent clock cycles, the voltage pump continues to deliver charge to the capacitor Cload until the voltage Vout equals the peak voltage occurring at node B. A simple negative voltage pump could be built from the circuit of
FIG. 1
by substituting pMos transistors for the two nMos transistors shown and moving their respective gate connections.
As supply voltage drops, charge pump efficiency decreases dramatically. When supply voltage drops to approximately 1.8 volts, efficiency of the charge pumps drops to around 15 percent. That means it takes six mA of supply voltage (Vcc) current to supply one mA of pumped voltage (Vccp) current. Additionally, more array signals need to be boosted above the supply voltage to maintain desired array performance. Examples of signals which require boosting include the signal used to bias the bit lines (Bias), to equilibrate the sense amplifiers (EQ), and to isolate the sense amplifiers (ISO), which are signals well known to those of ordinary skill in the art.
For large parts, such as a memory having 256 megabits of storage, boosting all of those signals to Vccp approaches 8 mA of Iccp current, or 40 mA of Vcc current. That demand requires the use of much larger voltage pumps or more voltage pumps. Also, a wider bus is needed to carry the greater current demanded. Providing larger pumps or more pumps, as well as wider distribution buses, takes up valuable space. Additionally, different conditions place different demands on the boosted voltage Vccp. For example, during test modes, or refresh, there may be a much greater demand for the boosted voltage then during normal operation. Sizing voltage pumps to deliver the necessary increased voltage for these special situations results in inefficient operation of the voltage pump during normal operation. Accordingly, the need exists for a voltage pump which can deliver the necessary pumped voltages while at the same time maintaining a high degree of efficiency.
SUMMARY OF THE PRESENT INVENTION
The present invention solves the problems found in the prior art by providing two voltage pumps, or a single voltage pump having two pump circuits, with one pump or pump circuit having as its target value the normal pumped voltage Vccp and the other pump or pump circuit having as its target value an intermediate pumped voltage which is less than Vccp but still greater than the supply voltage Vcc. That intermediate pumped voltage may be referred to as Vcca.
With the intermediate pumped voltage Vcca at, for example, 0.8 volts above the supply voltage Vcc, or little more than an n-channel Vt above Vcc, the intermediate pumped voltage may be used quite effectively for Bias, EQ, ISO, or at any other point on the die that needs a pumped voltage, but not a pumped voltage as high as the 1.5-1.8 volts above Vcc that the access devices require. With the intermediate pumped voltage Vcca at about 0.8 volts above the supply voltage Vcc, pump efficiency returns to over 30 percent. By its very nature, less current is needed as the voltage delta is lower. On a part such as a 256 megabit design, an overall 10 percent of operating Vcc current will be saved. Additionally, fewer charge pumps will be needed. Bus size difference is very little, as the existing Vccp bus is cut into two buses at different potentials; one portion of the split bus being at the full pumped voltage Vccp while the other portion of the split bus is at the intermediate pumped voltage Vcca. Those advantages and benefits, and others, will become apparent from the Description of the Preferred Embodiments hereinbelow.
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Lebentritt Michael S.
Micro)n Technology, Inc.
Phung Anh
Thorpe Reed & Armstrong LLP
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