Interlocking via for package via integrity

Details Interlocking via for package via integrity Interlocking via for package via integrity

2007-03-13

2007-03-13

Hoang, Quoc (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S621000, C257SE23142, C438S622000, C438S508000

Reexamination Certificate

active

11023750

ABSTRACT:
A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric layer extending from a surface of the dielectric layer to the first conductive layer; providing a recess in the first conductive layer and in communication with the hole to provide an interlocking volume under the dielectric layer; providing a conductive material in the hole and in the recess to form a package via having an interlocking section in the interlocking volume of the recess; and providing a conductive material on the dielectric layer to form a second conductive layer adapted to be in electrical contact with the first conductive layer through the package via.

REFERENCES:
patent: 6800549 (2004-10-01), Lee
patent: 2003/0194872 (2003-10-01), Parikh et al.
patent: 2005/0277281 (2005-12-01), Dubin et al.

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