Interlocking memory/logic cell layout and method of manufacture

Details Interlocking memory/logic cell layout and method of manufacture Interlocking memory/logic cell layout and method of manufacture

2007-10-02

2007-10-02

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S069000, C365S072000

Reexamination Certificate

active

11585460

ABSTRACT:
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

REFERENCES:
patent: 6370052 (2002-04-01), Hsu et al.
patent: 6704216 (2004-03-01), Cheng et al.

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