Interlocking and invertible semiconductor device tray and test c

Details Interlocking and invertible semiconductor device tray and test c Interlocking and invertible semiconductor device tray and test c

1994-02-04

1996-02-20

Gehman, Bryon P.

Special receptacle or package

Holder for a removable electrical component

For a semiconductor wafer

206509, 206563, 206725, B65D 8542, B65D 2100

Patent

active

054922232

ABSTRACT:
A tray (10') for handling a semiconductor device encapsulated in a package body and having multiple electrical I/Os projecting from the package body has cell-to-cell interlocking capability as well as invertibility. An interlocking nest feature (16) is formed on the underside of the tray and interfaces with the cells (12') on the topside of the tray (10') when the trays are stacked. The interlocking nest feature has an external chamfer (20) which mates with a lead-in chamfer (18) of the tray cell to align the interlocking feature (16) and the cell (12'). The interlocking nest feature (16) has an internal device retaining chamfer (22) and a device capture surface (26) to guide and retain the semiconductor device when stacking trays, inverting trays or processing semiconductor devices with the trays inverted. In-tray inspection and electrical test are also possible using a test contactor having a functional equivalent of the interlocking nest feature.

REFERENCES:
patent: 3454921 (1969-07-01), Coleman et al.
patent: 3552548 (1971-01-01), Wallestad
patent: 3672495 (1972-06-01), Bauer et al.
patent: 3746157 (1973-07-01), l'Anson
patent: 4703984 (1987-11-01), Mitchell, Jr.
patent: 5103976 (1992-04-01), Murphy
patent: 5155902 (1992-10-01), Fierkens
25.times.25 OMPAC TRAY drawing by ITW Camtex, 15 Jul. 1993.
300 MIL TSOP TYPE II 176 POCKET tray drawing by ITW Camtex, 1 Sep. 1992.

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