Electrical computers and digital processing systems: processing – Byte-word rearranging – bit-field insertion or extraction,...
Reexamination Certificate
2011-06-21
2011-06-21
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Byte-word rearranging, bit-field insertion or extraction,...
C712S220000
Reexamination Certificate
active
07966482
ABSTRACT:
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
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Eitan Benny
Mennemeier Larry M.
Mittal Millind
Peleg Alexander
Yaari Yaakov
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Kenneth S
LandOfFree
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