Interleaving operations in a floating-point numeric processor

Details Interleaving operations in a floating-point numeric processor Interleaving operations in a floating-point numeric processor

1992-07-10

1993-04-20

Mai, Tan V.

Boots, shoes, and leggings

364754, G06F 738

Patent

active

052048292

ABSTRACT:
A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.

REFERENCES:
patent: 4999801 (1991-03-01), Katsuno
Taylor, "Radix 16 SRT dividers with overlap quotient selection stages", IEEE, Sep. 1985, pp. 64-71.
Montoye et al., "Design of the IBM RISD system/6000 floating-point execution unit," IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, pp. 59-70.
Birman et al., "Developing the WTL 3170/3171 Spare Floating-Point Coprocessors", IEEE/Feb. 1990, pp. 55-63.
Steiss et al., "A 65 MHz Floating Point Coprocessor for a RISE Processor," IEEE, Mar. 1991, pp. 60-61, 94-95 & 250.

Affiliated with

Also associated with

Rating

Interleaving operations in a floating-point numeric processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaving operations in a floating-point numeric processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaving operations in a floating-point numeric processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1530500