Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2006-08-29
2006-08-29
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230030, C365S189020, C365S236000, C711S149000, C711S157000
Reexamination Certificate
active
07099231
ABSTRACT:
A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.
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Au Mario
Lin Lan
Ma Ta-Chung
Mo Jason Z.
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Tran Andrew Q.
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