1986-05-13
1988-05-03
Fleming, Michael R.
Excavating
371 37, G06F 1110
Patent
active
047425172
ABSTRACT:
In an interleaving circuit, writing and reading are executed on the two dimonsional array memory according to a first address sequence and a second address sequence, and product code errors occurring on the same column are propagated to the columns which are different with each other. The errors are thereby scattered to minimize the decreasing of the error correcting capability of the product codes.
REFERENCES:
patent: 4394642 (1983-07-01), Currie
patent: 4534031 (1985-08-01), Jewer
patent: 4559625 (1985-12-01), Berlekamp
patent: 4631725 (1986-12-01), Takamura
patent: 4633471 (1986-12-01), Perasa
Satoh Isao
Sugimura Tatsuo
Takagi Yuji
Fleming Michael R.
Matsushita Electric - Industrial Co., Ltd.
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