Interleaving block operations employing an instruction set capab

Details Interleaving block operations employing an instruction set capab Interleaving block operations employing an instruction set capab

1995-11-20

1998-06-02

Kim, Matthew M.

395380, 395484, G06F 930, G06F 1200, G06F 1300

Patent

active

057614725

ABSTRACT:
A computer system which includes a processor having an instruction set capable of "delaying" block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps which exploits the characteristics of the instruction set and architecture of the processor in order to increase efficiency and throughput of the computer system is provided. Hence by interleaving the block-store instruction of the previous data block with the block-load instruction of the next data block, the entire block transfer process can streamlined.

REFERENCES:
patent: 5455918 (1995-10-01), Fowler et al.
patent: 5475823 (1995-12-01), Amerson et al.
patent: 5504869 (1996-04-01), Uchida

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