Interleavement for transport of frames and cells

Details Interleavement for transport of frames and cells Interleavement for transport of frames and cells

2000-08-10

2004-08-31

Kizou, Hassan (Department: 2662)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395700, C370S444000, C710S027000, C710S028000

Reexamination Certificate

active

06785284

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communication systems and, in particular, to an improved direct memory access (DMA) handler for an Internet Protocol (IP) over asynchronous transfer mode (ATM) system.
2. Description of the Related Art
The Internet Protocol (IP) is one of the most popular networking protocols in use today. Briefly, IP encapsulates data into packets or frames of varying length. However, IP does not provide true quality of service (QoS), which is a requirement of multimedia messaging. Asynchronous transfer mode (ATM) systems pack data into equal length cells and also provide for true QoS.
Systems that employ IP over ATM must therefore provide for handling of the varying length IP frames and the fixed length ATM cells without doing violence to the ATM QoS requirements. One approach is to receive the IP frames, disassemble them, and reassemble them as ATM cells. This does not necessarily provide an optimal result, however.
As such, there is a need for an improved system for handling IP frames and ATM cells.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a direct memory access device (DMA) in accordance with the present invention. Briefly, the DMA device supports data transfers from multiple requesters over a shared media by interleaving frames and cells.
A DMA controller according to an implementation of the present invention includes a bus driver, a bus sniffer, a priority controller and a context machine. The bus sniffer is used to identify a cast type of a transfer on the bus, i.e., whether the transfer is a frame or cell transfer. The priority controller asserts a signal allowing access to the bus. The context machine stores system context. The controller supervises interleaving of frames and cells on the bus and asserts a frame end signal when a frame has been transmitted.


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