Interleaved wordline architecture

Details Interleaved wordline architecture Interleaved wordline architecture

2002-01-31

2004-02-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S072000, C365S051000, C365S052000, C365S149000, C365S190000, C365S208000

Reexamination Certificate

active

06687146

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to DRAM memories. More particularly the invention relates to a high packing density folded bitline DRAM memory array architecture.
BACKGROUND OF THE INVENTION
Aggressive development in dynamic random access memory (DRAM) fabrication processes and the small DRAM cell size makes commodity DRAM the highest density memory today. The high density of DRAM makes it very attractive for portable electronic devices that require large amounts of memory, but in a relatively small package. A further development is full integration of electronic components onto a single silicon chip. Examples of this include application specific integrated circuits (ASIC) that pack logic functions, DSP's, microcontrollers and memory onto a single semiconductor chip. In most ASIC applications, memory tends to occupy a relatively large percentage of area, therefore it is desirable to minimize the amount of area occupied by the integrated memory.
It is well known to practitioners in the art that a single DRAM memory cell typically includes an n-channel or p-channel access transistor connected in series to a storage capacitor. The storage capacitor can be of the stacked, trench or planar type. Of the three types, a DRAM using planar type storage capacitors is the least expensive to manufacture, whereas the stacked and trench capacitor processes require additional complex steps over planar storage capacitor DRAM processes. Although stacked and trench capacitor DRAM's are found in commodity DRAM devices, they are less prevalent in highly integrated chips such as ASICs. This is because current manufacturing processes optimized for trench and stacked capacitor DRAM memory are not optimized for logic circuits. Similarly, manufacturing processes optimized for logic are not optimized for DRAM memory. Therefore, devices manufactured with one optimized process will either have memory or logic circuits operating at sub-standard performance levels. Although hybrid DRAM/logic processes have been developed, they are still relatively expensive and do not allow the memory and logic circuits to perform at their full potential.
Since planar capacitor DRAM processes are very similar to standard logic manufacturing processes, ASIC devices integrating logic with planar capacitor DRAM benefit from less expensive manufacturing costs and high performance from both logic circuits and memory. However, the reduced manufacturing cost for planar capacitor type dynamic memory is offset by the relatively poor packing density of its cells, resulting in DRAM arrays of lower density than memory arrays employing stacked or trench capacitors for the same area. Trench and stacked capacitor cells have storage capacitors built vertically relative to the semiconductor substrate to reduce the surface area occupied by the cell. Planar capacitor cells on the other hand, require large amounts of semiconductor surface area because their capacitor plates are formed on the same plane as the substrate surface.
There are two widely used DRAM memory array layout architectures, called open bitline and folded bitline architectures. Examples of the folded bitline architecture are shown in
FIGS. 1 and 2
, and an example of the open bitline architecture is shown in FIG.
3
. Both architectures illustrate the arrangement of bitline sense amplifiers (BLSA), bitlines, planar capacitor memory cells and wordlines (WL) with respect to each other.
The schematic of
FIG. 1
illustrates the poor packing density of planar capacitor cells arranged in a folded bitline architecture. In this particular example four bitlines, ten wordlines labelled as WL to WL+9, and a corresponding number of memory cells are shown. The folded bitline architecture of
FIG. 1
will now be described. Each BLSA
10
is connected to a pair of complementary bitlines
12
and
14
, labelled as BLi, BLi* and BLi+1, BLi+1*, which extend in parallel from one side of BLSA
10
. Planar capacitor cells
16
are connected to each of the bitlines
12
and
14
via a respective bitline contact
18
. Bitlines
12
and
14
are typically formed of aluminum above the cells
16
and polysilicon wordlines
24
. Each cell
16
includes a cell plate diffusion, or active area
20
and an access transistor active area
22
. Polysilicon wordlines
24
run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas
22
of any cell
16
in their path. The cells
16
connected to the same wordline are commonly referred to as a row of memory cells. It should be noted that only the diffusion areas of the cells
16
are shown to simplify the figure, however, those of skill in the art will understand that a thin oxide dielectric layer covers each cell plate active area
20
, which is then covered by a polysilicon layer acting as a capacitor plate. Those of skill in the art will also understand that prior to the deposition of the polysilicon wordlines
24
, transistor gate oxides are formed over the memory cell access transistor channel regions. Planar capacitor cell fabrication methods are well known in the art, and do not require further discussion. The cells
16
of each row are interleaved with an adjacent row of cells
16
to maximize the packing density of the cells along the bitline direction. However, passing wordlines that run between two back-to-back cells
16
, as shown in areas
26
, limit the extent to which the cells can be packed together. There is the added disadvantage that the wordlines are formed of polysilicon, which has relatively high resistivity when compared to metal. Titanium or tungsten silicided wordlines have been used to reduce the effective resistance of the polysilicon wordlines, however, they are still more resistive than aluminum interconnections. Therefore this higher resistivity slows memory access times.
A solution proposed in the prior art to increase memory cell packing density along the wordline direction for folded bitline architectures is shown in FIG.
2
. The architecture is almost identical to the architecture shown in
FIG. 1
, except for the shape of the memory cells. In
FIG. 2
, each memory cell includes a rectangular shaped cell plate active area
21
and an access transistor active area
22
. Polysilicon wordlines
24
run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas of all cells in their path. It is noted that each pair of memory cells sharing the same bitline contact form a “C” shape. Complementary bitlines
12
and
14
are connected to each bitline sense amplifier
10
, and each bitline makes contact to a plurality of cells. To save space, every alternate row of “C” shaped pair of memory cells has its pairs of memory cells rotated by 180 degrees. This way, the bitline contacts
18
in a column are offset with each other, allowing the complementary bitlines to be placed closer together. Unfortunately, this arrangement results in a poor cells/bitline ratio, and as with the architecture shown in
FIG. 1
, the long polysilicon wordlines slow the memory access time.
The schematic of
FIG. 3
illustrates planar capacitor memory cells arranged in an open bitline architecture. All the elements shown in
FIG. 3
are identical to those described in
FIG. 1
, except that they are arranged differently. More specifically, the complementary pair of bitlines
12
and
14
extend from opposite sides of BLSA
10
. Now there are no passing wordlines, and a memory cell packing density higher than that for the folded bitline architecture shown in
FIG. 1
is achieved. In addition, a polysilicon top cell plate
28
is shown overlayed upon the cell plate diffusion areas
20
of the cells connected to wordlines WL+5 and WL+6. Similar top cell plates are formed over all the cell plate diffusion areas
20
, but not shown in
FIG. 3
to simplify the schematic. However, unbalanced noise in a complementary pair of bitlines is a problem that is undesired because an activated wordline capacitively couples to all t

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