Interleaved synchronous bus access protocol for a shared memory

Details Interleaved synchronous bus access protocol for a shared memory Interleaved synchronous bus access protocol for a shared memory

1985-11-22

1989-01-10

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1314

Patent

active

047978155

ABSTRACT:
A system for sharing several memory modules by several processors on a common bus uses a protocol in which, after a processor gains access to a memory module read or write data is transferred on the bus within a preset number of system clock periods. After priority is established by polling, the processor sends memory address on the common bus. For each operation several idle system clock periods are provided before data is returned from the memory to permit the memory to retrieve the data. Meanwhile, the protocol interleaves requests for access to other memory modules from other processors thereby increasing the throughput of the system.

REFERENCES:
patent: 3997896 (1976-12-01), Cassarino Jr. et al.
patent: 4181974 (1980-01-01), Lemay
patent: 4669056 (1987-05-01), Waldecker et al.

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