Interleaved memory program and verify method, device and system

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185240

Reexamination Certificate

active

08004897

ABSTRACT:
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.

REFERENCES:
patent: 5532964 (1996-07-01), Cernea et al.
patent: 5574684 (1996-11-01), Tomoeda
patent: 5666323 (1997-09-01), Zagar
patent: 5901100 (1999-05-01), Taylor
patent: 6178129 (2001-01-01), Chen
patent: 6215705 (2001-04-01), Al-Shamma
patent: 6456542 (2002-09-01), Roohparvar
patent: 6590808 (2003-07-01), Yamada et al.
patent: 6636444 (2003-10-01), Uchida et al.
patent: 6714475 (2004-03-01), Huber
patent: 6751121 (2004-06-01), Marotta
patent: 6768688 (2004-07-01), Mihara
patent: 6917543 (2005-07-01), Sato
patent: 6920522 (2005-07-01), Roohparvar
patent: 6950337 (2005-09-01), Bellini et al.
patent: 7006382 (2006-02-01), Pekny et al.
patent: 7073016 (2006-07-01), Zitlaw
patent: 7120055 (2006-10-01), Kessenich
patent: 7130222 (2006-10-01), Ho et al.
patent: 7539062 (2009-05-01), Doyle
patent: 2004/0156235 (2004-08-01), Bellini et al.
patent: 2005/0185501 (2005-08-01), Lee et al.
patent: 2006/0083097 (2006-04-01), Frulio et al.
patent: 2006/0187716 (2006-08-01), Roohparvar
patent: 2006/0209592 (2006-09-01), Li et al.
patent: 2006/0227618 (2006-10-01), Lee
patent: 2006/0245270 (2006-11-01), Louie et al.
patent: 2006/0245272 (2006-11-01), Hartono et al.
patent: 2007/0011581 (2007-01-01), Nakanishi et al.
patent: 2007/0070704 (2007-03-01), Ho et al.
patent: 2009/0231918 (2009-09-01), Doyle
International Search Report for International Application No. PCT/US2007/088343 mailed Apr. 21, 2008, 3 pages.
International Written Opinion for International Application No. PCT/US2007/088343 mailed Apr. 21, 2008, 5 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interleaved memory program and verify method, device and system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaved memory program and verify method, device and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved memory program and verify method, device and system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2740995

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.