Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-12-16
2009-11-03
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230080, C365S230010
Reexamination Certificate
active
07613070
ABSTRACT:
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. In another embodiment, the command path includes a plurality of command latches that latch commands from the input signals in an interleaved manner and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner.
REFERENCES:
patent: 4695952 (1987-09-01), Howland
patent: 5261068 (1993-11-01), Gaskins et al.
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5410680 (1995-04-01), Challa et al.
patent: 6044429 (2000-03-01), Ryan et al.
patent: 6415340 (2002-07-01), Ryan et al.
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6564285 (2003-05-01), Mills et al.
patent: 6571307 (2003-05-01), Kuo et al.
patent: 6614691 (2003-09-01), Roohparvar
patent: 6724686 (2004-04-01), Ooishi et al.
patent: 6807598 (2004-10-01), Farmwald et al.
patent: 6907493 (2005-06-01), Ryan
patent: 6928024 (2005-08-01), Pfeiffer et al.
patent: 7080275 (2006-07-01), Abedifard et al.
patent: 2001/0024135 (2001-09-01), Harrison
patent: 2001/0033245 (2001-10-01), Campanale et al.
patent: 2002/0003747 (2002-01-01), Yahata et al.
patent: 2002/0016884 (2002-02-01), Ryan et al.
patent: 2002/0054516 (2002-05-01), Taruishi et al.
patent: 2002/0136063 (2002-09-01), Keeth et al.
patent: 2003/0196078 (2003-10-01), Wise et al.
patent: 2004/0052138 (2004-03-01), Penney
patent: 2006/0095808 (2006-05-01), Abedifard et al.
patent: 2006/0133126 (2006-06-01), Fujisawa et al.
patent: 2006/0253665 (2006-11-01), Mailloux et al.
patent: 2008/0080291 (2008-04-01), Ha
Dorsey & Whitney LLP
Le Thong Q
Micro)n Technology, Inc.
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