Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2001-12-28
2003-08-05
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
C341S051000, C341S059000, C341S050000
Reexamination Certificate
active
06603412
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to channel encoding and decoding, and more particularly to interleaved codes such as turbo codes with iterative decoding and related systems.
2. Background
Demand for wireless information services via cell phones, personal digital assistants (PDAs), and Internet appliances (IA) plus wireless networking among notebook computers is rapidly growing. However, the air interface in wireless communication typically has a large bit error rate due to effects such as noisy channels with multipath fading.
Channel coding for the air interface transmission channel using CDMA (code division multiple access) together with reception schemes such as rake detectors help mitigate the error rate. In particular, third generation wireless proposals include channel coding of data packets with rate ⅓ turbo codes. Turbo codes are parallel concatenated convolutional codes with an interleaving between the parallel codes.
FIG. 2
a
illustrates the wireless standard UMTS/3GPP turbo encoder (the trellis termination connections have been omitted for clarity). The interleaver essentially randomly permutes the input data within a block; this permutation underlies the good coding performance because close together inputs bits are spread apart by the interleaving.
Cascade architectures for Viterbi decoders have been described in Feygin et al, Generalized Cascade Viterbi Decoder—a Locally Connected Multiprocessor with Linear Speed-Up, Proc. ICASSP-91 1097 (1991) and Black et al, A Unified Approach to the Viterbi Algorithm State Metric Update for Shift Register Processes, Proc. ICASSP-92 V-629 (1992). Viterbi decoding can be applied to Turbo codes.
FIG. 2
b
illustrates an iterative MAP (maximum a posteriori probability) decoder consisting of repeated applications of computations based on the trellises of the two constituent convolutional codes and the interleaver of the encoder of
FIG. 2
a.
MAP decoding is more complex than but provides better performance than Viterbi decoding. U.S. Pat. No. 6,023,783 (Divsalar) discloses various turbo encoders and decoders, and Hagenauer et al, Iterative Decoding of Binary Block and Convolutional Codes, 42 IEEE Tr.Info.Th. 429 (1996) describes the soft iterative MAP decoding.
SUMMARY OF THE INVENTION
The present invention provides an interleaver architecture with memory partitioning into banks to allow quasi-parallel memory read/writes.
This has advantages including preferred embodiments with faster or simpler turbo encoding/decoding.
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Dabak Anand
Gatherer Alan
Linn John
Schmidl Timothy M.
Brady W. James
Hoel Carlton H.
Mai Lam T
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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