Interleaved cache for multiple accesses per clock cycle in a mic

Details Interleaved cache for multiple accesses per clock cycle in a mic Interleaved cache for multiple accesses per clock cycle in a mic

1994-02-02

1996-09-24

Swann, Tod R.

Boots, shoes, and leggings

395484, 395454, 395457, 364DIG1, G06F 1208

Patent

active

055599869

ABSTRACT:
An interleaved cache is used for multiple data accesses per clock in a microprocessor. The cache includes a storage array having multiple banks of single-ported memory cells for storing data, a bank selector for selecting banks in the storage array simultaneously according to the multiple data accesses, and a datapath for transfering data between execution units in the microprocessor and the storage array. The cache of the present invention also includes contention logic for prioritizing the multiple data accesses when multiple data accesses are to be same bank.

REFERENCES:
patent: 4783736 (1988-11-01), Ziegler et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 5043874 (1991-08-01), Gagliardo et al.
patent: 5168547 (1992-12-01), Miller et al.
patent: 5179680 (1993-01-01), Colwell et al.

Affiliated with

Also associated with

Rating

Interleaved cache for multiple accesses per clock cycle in a mic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaved cache for multiple accesses per clock cycle in a mic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved cache for multiple accesses per clock cycle in a mic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1947681