Interleaved auto-zero analog-to-digital converter with...

Details Interleaved auto-zero analog-to-digital converter with... Interleaved auto-zero analog-to-digital converter with...

1998-03-24

2001-04-17

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S118000, C327S065000

Reexamination Certificate

active

06218975

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an analog-to-digital converter which converts an analog signal to a digital signal, and more particularly, an IAZ (Interleaved Auto-Zero) analog-to-digital converter.
BACKGROUND OF THE INVENTION
A parallel analog-to-digital converter comprises a plurality of comparators for comparing an analog signal with an analog reference voltage, and an encoder for converting the signals output from the comparators to a digital signal.
The parallel analog-to-digital converter is superior to other types of analog-to-digital converters in terms of the analog-to-digital conversion speed.
FIG. 1
shows a first conventional parallel analog-to-digital converter which produces two output bits. Four resistors R are connected in series between a high-potential reference voltage VRH and a low-potential reference voltage VRL. The resistance value of the resistor at each end is set to one-half that of the other resistor.
Each of the nodes among the resistors is connected to one of two input terminals of each of three comparators CM
1
to CM
3
. Reference voltages VR
1
to VR
3
(which are obtained by division of the voltage difference between the reference voltages VRH and VRL by the resistances of the resistors R) are input, respectively, to the comparators CM
1
to CM
3
. An analog input signal Vin is input to the other input terminal of each of the comparators CM
1
to CM
3
. The comparators CM
1
to CM
3
compare, respectively, the reference voltages VR
1
to VR
3
with the analog input signal Vin. When the analog input signal Vin has a potential higher than the corresponding reference voltage VRl to VR
3
, the comparators CM
1
to CM
3
output, respectively, high-level output signals SG
1
to SG
3
. In contrast, when the analog input signal Vin has a potential lower than the corresponding reference voltage VR
1
to VR
3
, the comparators CM
1
to CM
3
output, respectively, low-level output signals SG
1
to SG
3
.
If the analog input signal Vin has a potential higher than the reference voltage VR
2
and a potential lower than the reference voltage VR
3
, the comparators CM
1
and CM
2
output the output signals SG
1
and SG
2
high, and the comparator CM
3
outputs the output signal SG
3
low. The output signals SG
1
to SG
3
form a thermometer code.
An encoder
3
receives the signals SG
1
to SG
3
and outputs two bits of digital output signals D
0
, D
1
. A control circuit
4
controls the timing of the comparators CM
1
to CM
3
and the encoder
3
.
To ensure the accuracy of conversion regardless of a variation in the characteristics of the underlying transistors of the circuit, the comparators CM
1
to CM
3
preferably comprise, respectively, chopper type comparators. In the case of a CMOS comparator, an input offset voltage varies from comparator to comparator because of a variation in the characteristics of the MOS transistors. Such comparators produces an insufficiently accurate comparison result because of the variance in the input offset voltage.
FIG. 2
is a circuit diagram of the chopper type comparator. The input terminals, which receive the analog input signal Vin and the reference voltage VR, are connected to a node N
1
(first terminal of a capacitor
1
) via switching circuits SW
1
and SW
2
. The switching circuits SW
1
and SW
2
are turned on in response to the control signals C
1
and /CZ high. The second terminal of the capacitor
1
(a node N
2
) is connected to an input terminal of an inverter circuit
2
a
. Input and output terminals of the inverter circuit
2
a
are connected to each other via a switching circuit SW
3
. The switching circuit SW
3
is turned on in response to the control signal CZ high.
In an auto-zero operation, the input and output terminals of the inverter circuit
2
a
are reset to a threshold value of the inverter circuit
2
a
. The output terminal of the inverter circuit
2
a
is connected to an input terminal of an inverter circuit
2
c
via an inverter circuit
2
b
and a switching circuit SW
4
. The switching circuit SW
4
is turned on in response to the control signal /CF high. The signal output from the inverter circuit
2
c
is inverted by an inverter circuit
2
e
and output as a signal OUT. Further, the signal output from the inverter circuit
2
c
is fed back to the inverter circuit
2
c
via an inverter circuit
2
d
and a switching circuit SW
5
. The switching circuit SW
5
is turned on in response to the control signal CF high.
The operation of the chopper type comparator will be described with reference to FIG.
3
. First, when the control signal C
1
goes high, and the control signal /CZ goes low, through the auto-zero operation, the node N
2
is reset to the threshold value of the inverter circuit
2
a
, so that a charging current flows into the capacitor
1
, thereby increasing the potential of the node N
1
to the reference voltage VR. Subsequently, when the control signal C
1
goes low, and the control signals /CZ and /CF go high, the analog input signal Vin is compared with the reference voltage VR. If the analog input signal Vin has a potential higher than the reference voltage VR, the potential of the node N
2
becomes higher than the threshold value of the inverter circuit
2
a
as a result of capacitive coupling of the capacitor
1
. In contrast, if the potential of the analog input signal Vin is lower than the reference voltage VR, the potential of the node N
2
becomes lower than the threshold value of the inverter circuit
2
a
. Since the switching circuit SW
4
is turned on at this time, the signal output from the inverter circuit
2
a
is provided to the inverter circuit
2
c
via the inverter circuit
2
b
and the switching circuit SW
4
. The signal output from the inverter circuit
2
c
is output as the signal OUT via the inverter circuit
2
e.
Next, when the control signal C
1
goes high again, and the control signals /CZ and /CF go low, the potential of the node N
1
is reset to the reference voltage VR. Through the auto-zero operation performed by the inverter circuit
2
a
, the potential of the node N
2
is reset to the threshold value of the inverter circuit
2
a
. At this time, the switching circuit SW
5
is turned on, so that the inverter circuits
2
c
and
2
d
form a latch circuit which latches the signal OUT.
The chopper type comparator alternately performs the auto-zero operation and the comparing operation. Accordingly, one-half of the time required for the converting operation is spent on the auto-zero operation, thereby decreasing the conversion speed. Increasing the frequencies of the control signals C
1
, CZ, /CZ, CF, and /CF makes it difficult to perform the auto-zero operation and the comparing operation. Accordingly, it is not easy to increase the conversion speed of analog-to-digital conversion by increasing the frequencies of the control signals C
1
, CZ, /CZ, CF, and /CF.
If the number of comparators is increased in order to increase the number of bits of the digital output signal, noise is apt to arise in the reference voltage VR, the analog input signal Vin, and the power source which causes erroneous operation of the comparator. At the time of the auto-zero operation a charge/discharge current simultaneously flows between the reference voltage VR and the capacitor C
1
, and the input and output terminals of the inverter circuit
2
a
are concurrently reset to the threshold value. Consequently, a through current simultaneously flows through the inverter circuits
2
a
. Furthermore, at the time of the comparing operation, a charge/discharge current simultaneously flows between the analog input signal Vin and of each of the capacitors
1
.
To increase the conversion speed of the chopper type comparator, a technique of controlling the control signals C
1
, CZ, /CZ, CF, and /CF at the timing shown in
FIG. 4
has been proposed. More specifically, after the auto-zero operation, the control signals C
1
, CZ, and /CZ are maintained in the state of a comparing operation, and the control signals CF and /CF are inverted several times to thereby s

Affiliated with

Also associated with

Rating

Interleaved auto-zero analog-to-digital converter with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaved auto-zero analog-to-digital converter with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved auto-zero analog-to-digital converter with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2501068