Interleaved analog tracking timing and gain feedback loops for p

Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

360 51, 375345, 375362, G11B 509

Patent

active

061634204

ABSTRACT:
A high speed analog timing and gain feedback control methods and a low power analog tracking timing and gain feedback apparatus are provided for data detection, such as, partial-response maximum-likelihood (PRML) data detection in a direct access storage device (DASD). The interleaved gain and timing tracking control circuit includes an even interleave gain and timing tracking control providing an even interleave gain error signal and an even interleave timing error signal; and an odd interleave gain and timing tracking control providing an odd interleave gain error signal and an odd interleave timing error signal. The even interleave gain error signal and the odd interleave gain error signal are combined to provide a resulting gain control signal. The even interleave timing error signal and the odd interleave timing error signal are combined to provide a resulting timing control signal. The resulting gain control signal is applied to a variable gain amplifier and the resulting timing control signal is applied to a variable clock circuit in a data channel of a direct access storage device (DASD).

REFERENCES:
patent: 5424881 (1995-06-01), Behrens et al.
patent: 5459757 (1995-10-01), Minuhin et al.
patent: 5521945 (1996-05-01), Knudson
patent: 5729396 (1998-03-01), Dudley et al.
patent: 5796358 (1998-08-01), Shih et al.
patent: 6005729 (1999-12-01), Poss
patent: 6005730 (1999-12-01), Poss
IBM Patent Application R0997-051, "Low Power Analog Signal Processing Circuit", By Joe M. Poss, Ser. No. 08/891,517 filed Jul. 11, 1997.
IBM Patent Application R0997-052, "Analog Signal Processing Circuit with Integrated Gain and Timing Error Signal Processing", By Joe M. Poss Ser. No. 08/891,378 filed Jul. 11, 1997.
IBM Patent Application R0997-053, "Signal Error Generating Circuit for an Analog Signal Processing Channel", By Joe M. Poss Ser. No. 08/891,489 filed Jul. 11, 1997.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interleaved analog tracking timing and gain feedback loops for p does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaved analog tracking timing and gain feedback loops for p, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved analog tracking timing and gain feedback loops for p will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-275578

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.