Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-06-23
1999-10-26
Hoang, Huan
Static information storage and retrieval
Floating gate
Multiple values
36518518, 365184, G11C 1604
Patent
active
059739584
ABSTRACT:
An interlaced storage method for storing data in multi-level flash memory cells so that data bits from multiple addresses are encoded and stored in a single flash memory cell, and a method for reading and decoding the stored data. In the method for storing data, the data bit values for each address are multiplied by a weight having a greater value for each successively higher address to provide weighted bit values. The weighted bit values for the same order bits from the addresses are then added together to provide results, each result being programmed as a threshold voltage vt in a flash memory cell. To read the stored data, a weight comparison is set equal to the greatest weight and compared with the vt value in a first pass. If the vt value is equal to the weight comparison value, the data bits represented by the vt value are identified. If the vt value is greater than the weight comparison value, the most significant bit stored is identified as a "1" and the next lower weight is added to the weight comparison value for a second pass. If the vt value is less than the weight comparison value, the most significant bit stored is identified as a "0" and the next lower weight is subtracted from the weight comparison value for a second pass. Second and subsequent passes proceed in a similar manner with either all bits being identified, or only one bit identified and the weight comparison value being modified for a next pass. Passes proceed until all bits are identified.
REFERENCES:
patent: 5680343 (1997-10-01), Kamaya
patent: 5721701 (1998-02-01), Ikebe et al.
patent: 5815436 (1998-09-01), Tanaka et al.
Advanced Micro Devices , Inc.
Hoang Huan
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