Interlaced multi-level memory

Details Interlaced multi-level memory Interlaced multi-level memory

2000-03-01

2004-03-16

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185200, C365S185240

Reexamination Certificate

active

06707713

ABSTRACT:

BACKGROUND
A flash memory cell can be a field effect transistor (FET) that includes a select gate, a floating gate, a drain, and a source. A cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched on and off.
Flash memory cells include NAND type and NOR type circuits. NAND flash memory cells have “n” cell transistors connected in series and are connected in parallel between bit lines and ground lines. NAND flash memory cells are useful in large scale integration. NOR flash memory cells include cell transistors that are connected in parallel between bit lines and ground lines. NOR flash memory cells provide high-speed operation.
Programming a cell includes trapping excess electrons in the floating gate to increase voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The cell is programmed when the cell current is less than a reference current when the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.
Memory cells with only two programmable states contain only a single bit of information, such as a “0” or a “1”. A multi-level cell (“MLC”) is a cell that can be programmed with more than one voltage level. Each voltage level is mapped to corresponding bits of information. For example, a single multilevel cell can be programmed with one of four voltage levels, e.g. −2.5V, 0.0V, +1.0V, +2.0V that correspond to binary bits “00”, “01”, “10”, and “11”, respectively. A cell that is programmable at more voltage levels can store more bits of data based on Eqn. 1.
N=
2
B
  Eqn.1
B is the number of bits of data stored
N is the number of voltage levels.
The amount of data stored in a cell can be increased by using more programming states. Thus, two or more bits of data are stored in each cell. A cell with four states requires three threshold levels. U.S. Pat. Nos. 5,043,940 and 5,172,338 describe such cells and are incorporated herein by reference. More time is required to program a cell with more states to avoid overshooting a desired smaller programming range.
FIG. 1
shows a diagram of a multi-level cell's programming voltage levels
100
with four voltage distributions (“programming voltage levels”)
102
,
104
,
106
, and
108
. For illustration purposes, the voltage distributions
102
104
,
106
, and
108
are referred to as “state A” “state B” “state C” and “state D”, respectively. They correspond to the two-bit binary values “00” “01” “10” and “11”, respectively.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS
A memory device having a plurality of multi-bit cells that are programmed with interlaced data provide superior read access time. The multi-bit cells are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage then reading the second bit of a first subset of the plurality of cells sequentially using a second reference voltage then reading the second bit of a second subset of the plurality of cells sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.


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