Interlaced memory matrix array having single transistor cells

Details Interlaced memory matrix array having single transistor cells Interlaced memory matrix array having single transistor cells

1975-07-10

1977-05-24

Trafton, David L.

Communications: electrical

Digital comparator systems

307238, 340173R, 340173FF, 357 45, 357 24, G11C 1300

Patent

active

040259072

ABSTRACT:
This disclosure relates to memory array organization of single transistor cells and the differential sense amplifiers provided therewith. To accommodate the differential sense amplifiers, the array is laid out in rows and functional columns where a functional column consists of a pair of columns such that odd row cells are connected to the odd column of the pair and even row cells are connected to the even column of the pair. A differential sense amplifier is then provided for each pair of odd and even columns which are inherently balanced at the sense amplifier terminals. Single ended or edge ended I/O circuitry is provided with direct access to the respective pairs of columns.

REFERENCES:
patent: 3771148 (1973-11-01), Aneshansley
patent: 3838295 (1974-09-01), Lindell
patent: 3852800 (1974-12-01), Ohwada et al.
patent: 3953839 (1976-04-01), Dennison et al.

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